Silicon Power XPOWER Zenith RGB DDR5 5600 32GB review

Memory (DDR4/DDR5) and Storage (SSD/NVMe) 372 Page 5 of 16 Published by

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Memory timings – a bit of theory about the basic parameters

Memory timings – a bit of theory about the basic parameters

The general rule is simple – the lower the number, the better the performance. When you look at the specs of a memory kit, for example, the one in this review, you will see something like CL40-40-40-76 1.25V. What does it mean? Well, this refers to CAS-TRCD-TRP-TRAS and CMD. These values are measured in clock cycles. 



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  • CAS latency (CL) – the number of cycles between sending a column address to the memory and the beginning of the data in response. The number of cycles to read the first bit of memory from a DRAM with the correct row already open. Unlike the other numbers, this is not a maximum but an exact number that must agree between the memory controller and the memory.
  • Row Address to Column Address Delay (TRCD) is the minimum number of clock cycles required to open a row of memory and access columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL.
  • Row Precharge Time (TRP) - the minimum clock cycles required to issue the precharge command and open the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL.
  • Row Active Time (TRAS) - the minimum clock cycles required between an active row command and issuing the precharge command. This is needed to refresh the row internally and overlaps with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + 2×CL.
 

 

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Command Rate (CR) - Now, 1T means it takes one clock cycle to “find” a memory bank, vs. 2T, where it takes two clock cycles to “find” the memory bank. Various factors depend on whether the chip selection can be executed in a single clock or needs two clocks. Among the most contributing factors appears to be the number of banks populated within the system from which the right bank has to be selected. The system already knows that all data must be in a single-bank configuration within this bank. If more banks are populated, there is an additional decision involved. 

 

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Determining the optimum timings can be very time-consuming, and it’s a matter of many attempts to achieve stability. Fine-tuning the above settings can bring some nice improvements. Especially Command Rate is commonly underestimated, as seen in our Ryzen RAM performance article. There are also some further timings, which most users leave for the motherboard to configure automatically. Still, they can be helpful if you’re joining the competition to beat some world records in SuperPi (but I’m not, so I always skip that part). 

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