Intel Cascade Lake AP: 48 cores with 12-channel DDR4 in multi-chip package
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Picolete
The Glue Team
schmidtbag
Before or after all the security mitigations? Before or after scheduler improvements? Because depending on your answer to those, the performance gap has already narrowed quite a bit (and the Windows scheduler still has a lot of tweaking necessary, including for Intel). Latency is currently AMD's Kryptonite, and if Intel is going to slap 2 cores together like this, that's going to have a hefty impact on their latency.
FOFINHO
That's so true! I only tought about it now.
xrodney
Not really, its about whole workflow process, not just simple instruction, but rather complete sequence of instructions and how much it is optimized. That's where cache,memory latency issues, flushing cache data, predictors, etc either positively or negatively affects IPC.
You can write application that do same operations and use same instructions and get totally different results (in terms of execution time).
And this is also where architecture specific optimizations can help but on other end can be abused for benchmarking (as we saw from intel few times).
H83
That´s the main and most important point of MCM but in this case Intel is doing this because they need something to compete against the 64 core Epyc CPU, nothing more. A true MCM CPU is probably reserved for their next arch.
How could i forget my amazing Core2Quad Q9550!
tunejunky
to quote Anthony Burgess ("A Clockwork Orange") "well, well, welly, well, well".
V A P O R W A R E in search of press
rl66
hmmm... The 1st copycat were AMD on this, Intel were the 1st to do this because next gen CPU wasn't ready and they needed a more high end CPU... It doesn't start few years ago with threadripper.
Well... As for AMD, i don't see a problem.
Also it was a proven method to do heavy CPU cheaper since several decade (from both AMD and Intel).
About the price, to have an idea my pair of CPU have cost around 7000 Euro, again it is not so expensive for a company (yeah, each one and i haven't paid myself 🙂 ) ... And right now it is the main target for this CPU.
rl66
Epyc is as the G34 in it's time... Dead before the start of the race... It's nearly impossible to get one outside selected country and if you get one the next chalenge is to get the hand on a mobo.
Despite lot of announcement for pro, the only move that AMD have done is more aviability in Radeon Pro: it is not enough... (can be a request in desguise).
JamesSneed
Just curious... What is Intel charging for this chip?
Picolete
And the TDP
Borys
Buy a XEON 48-core and win a Refrigerator to put the case in.... BEST DEAL EVER!
Picolete
They were testing if the chillers could cool this beast, they werent trying to reach 5ghz.
Koniakki
https://i.postimg.cc/hG3zxLvK/3-1080-725123810-2.png
user1
its not just multi socket, there will be two 24core dies (glued) on a single package (mcm) so 48cores with 12channels per socket.
the dual socket config for this platform is 96cores 24 channels.
also , tommorrow could be very interesting, this announcement seems preemptive against eypc 2 , i sense fear
vbetts
Moderator
Honestly how his this that much different from Ryzen in general? The CCX makeup up Zen in general are basically glued together by the Infinity Fabric on the dye.
user1
i think the biggest difference, is that ryzen was build from the ground up to be like this, the IF protocol is coherent across dies meaning, if a core on die 1 wants to access memory controller on die 0, it can do that almost directly, its alot like a Hypertransport bus.
Where as with intel it looks like they are just using their existant interconnect used between sockets on an mcm, which is fine, but likely has a higher latency penalty than zen due to additional hops (much like broadwell 22core cpus with the dual ring bus , but probably slower). numa support can reduce the penalty much like threadripper, but it's still not as good as a "native" interconnect
This is not great for intel thats for sure, instead of using just 1 expensive die, they now have to compete with 2 expensive dies (which in all likelyhood cost the same as the existing 10k xeons to make). against epyc 2 which is likely going to be priced as competitively as epyc 1.
edit: i think the simplest way to think of intel's approach as squeezing a 4p server onto 2p with some minor changes, where as zen is designed to be multi die natively.
Picolete
Rumors say that to reduce TPD, this CPUs wont have hyper threading
tunejunky
why do people still say "glued"? Intel's propaganda machine has already created a slapdash image that people who know better are using.
please do some basic research on Infinity Fabric, google should work.
Infinity Fabric made the hairs on the back of my neck stand on end when i first read the whitepaper. this is about as far from "glue" as technology can get.
this is an interposer of the highest order, a true quantum improvement in IC technology that will change our lives in the next ten years.
i say that with not one ounce of hyperbole, especially as most of us game as well.
Moore's Law is dead and this is the way forward.
Craigpd
In jest of Intel's borderline slander of AMD in some of their investor slides a few months back.
If someone would be so kind as to link the slidedeck, that would be fantastic. Phoneposting from work right now so hunting it down would be difficult for me.
Noisiv
is how Linpack should be run, and how AMD recommends it
Intel's HT is disabled as well
https://newsroom.intel.com/wp-content/uploads/sites/11/2018/11/cascade-lake-advanced-performance-press-deck.pdf
http://www.crc.nd.edu/~rich/CRC_EPYC_Cluster_Build_Feb_2018/Installing%20and%20running%20HPL%20on%20AMD%20EPYC.pdf
