JEDEC, the organization that develops standards for memory technologies, has revised its DDR5 memory specification under the new JESD79-5C standard. This update increases the maximum data transfer rate to 8800MT/s, up from the previous limit of 6400MT/s set in 2020. This adjustment aims to meet the evolving performance requirements of high-performance servers and technologies such as AI and machine learning. The JESD79-5C standard introduces significant enhancements in memory performance, reliability, and security.
Notably, it features the Per-Row Activation Counting (PRAC) system, which helps maintain data integrity by monitoring and managing activation frequencies at the wordline level of DRAM. This system can initiate a pause in system traffic and prompt mitigative actions when excessive activations are detected, ensuring more precise and reliable memory operation.
Other key updates in the JESD79-5C specification include:
- Expanded definition of timing parameters, now ranging from 6800 Mbps to 8800 Mbps.
- Extended DRAM core and Tx/Rx AC timings to accommodate the new speed limit.
- Introduction of Self-Refresh Exit Clock Sync, optimizing I/O training.
- Inclusion of Dual-Die Package (DDP) timings.
- Removal of Partial Array Self Refresh (PASR) due to security improvements.
These updates are designed to support the increasing demands for enhanced security and performance across various applications. The updated DDR5 SDRAM standard is available for download from the JEDEC website.
