TSMC starts development of 2nm process, 3nm already in the works
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Simen1
A single silicon atom is about 0,235 nm in diameter (nearest neigbour distance in a non stretched silicon lattice). So 2 nm is about 8-9 atoms wide. We are not at the end of the line yet! 😛
Denial
wavetrex
Denial
https://www.anandtech.com/show/14992/euv-demand-up-at-asml
https://www.eetimes.com/intel-says-euv-ready-challenging/
https://www.eetasia.com/tsmc-leading-the-way-in-euv-adoption/
https://www.anandtech.com/show/13683/intel-euvenabled-7nm-process-tech-is-on-track
There is literally a million articles about it
Intel purchased 10% of ASML back in 2012 specifically to get their foot in the door with EUV - they cut it, along with multiple other companies down to I think 2% now, but ASML is the only company that develops EUV tools and Intel is 100% using EUV for layers in it's 7nm process.
Kaarme
wavetrex
Ah, the fabled Intel 7nm...
...uuuhkay.
Can't wait to see an actual product made by it ;-)
But for now it's just bark and no bite.
craycray
CPC_RedDawn
I remember back in the days that magazines were a thing I used to read CustomPC magazine (hence my name CPC) which got consumed by bit-tech. But I remember them writing when we first got 65nm with I think it was conroe and the first Intel Core 2 CPU's. That the distance between each transistor in a 65nm CPU was 2000x thinner than a human hair...... Anyone want to clarify this? I always remembered that, its just one of those things.
cryohellinc
Denial
flashmozzg
Venix
ViperAnaf
"2nm"
EspHack
I wonder if we get a speed up when we go below the 1nm barrier, it seemed like going from 90nm to 60nm to 45nm was soo easy and quick, maybe bigger numbers make it go faster /s
Simen1
1nm is not a physical barrier. Its just in our minds. Aside from that its a good question. Capasitive effects are now dominating the total power, versus before 90 nm -ish. Back then it was the resistive loads that dominated power consumption. And power consumption is the thing that limits clock speeds. I guess clock speeds wont change much in the future, but signal distances may still shrink. Meaning that we may have more parallell throughput in the same area, given the constraints of power and clock speeds.
I.E. Expect larger caches with same clock speed but lower latencies, more cores, more AVX-like extentions, more GPU compute units, wider internal busses and such.
Astyanax
1nm is a physics problem.
schmidtbag
Astyanax
i wish quantum internet wasn't a physics problem 🙁
yasamoka