Ryzen 4000 desktop processors moved to 5nm+ process and released in late 2020

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A Zen 2 die has two CCX, each with 4 cores. Why is it weird they'd make it 8 cores and only one CCX? It would have the same size. Is that what AMD is planing? I don't know, but going bigger (physically) isn't a good idea for cost. Time will tell.
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Why is everyone being so negative? The title clearly states these will be 5nm+. Negative nancies 🙂 Have some belief, it'll be a good move from AMD.
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Maddness:

You don't really need to wait until next year. Current RyZens are kicking ass and chewing bubble gum. Performance per dollar is Stellar. There's probably never been a better time for an upgrade.
I was watching the rumors of Zen 3 and how amazing it'll be, even more versus Zen 2, and I told myself to wait 'til then; to grab the last hurrah of DDR4 with AMD's best and roll out for another 10 years. I'm not an upgrader. I buy something and I keep it until it's lifespan's out. My Motorola Moto G4 Plus phone is 3½ years old now. That gives you an idea. There's a reason why my current rig's mobo+CPU+SATA 3gb SSD are 10yo. I changed the other parts because: made sense to upgrade or replaced them or salvaged them for free for somewhere else. So, yeah. This rumor scares me.
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That would be crazy if this were true. I don't think this will contribute much toward the 15% IPC claim, though, I had my doubts about that in the first place. I could see how AMD might be pushing for 5nm, since that ought to make the 8-core CCX "sufficiently profitable". Remember, there are 2 problems with bigger dies: 1. The bigger it gets, the harder it is to get one in perfect condition (assuming the transistor size isn't what makes it bigger) 2. The bigger it gets, the less usable product you can fit on a wafer AMD's CCX design is so profitable because they could make a gargantuan and relatively affordable 64-core CPU with a relatively minimal performance penalty and minimal wasted silicon. The thing is, for the everyday user, the performance penalty from a 4-core CCX is significant, especially since Windows still hasn't fully figured it out properly (albeit, Linux isn't as good as it could be either, but it's still better). The bigger the CCX, the less likely data will be transmitted over the IF. Perhaps at 7nm, the 8-core CCX was just slightly too big on the silicon wafer to maximize profitability, but at 5nm the margins are probably adequate. So - I definitely predict that the 8-core CCX is where the bulk of the 15% IPC improvement comes in, and probably only for Windows desktop users. For everyone else, I'm sure the improvements will overall be less.
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I have read somewhere but don't remember where that Huawei is banned from getting 5nm from Tsmc and Amd is already have a contract for 5nm and now is taking a bigger piece of that Pie.Sry for my English.
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Guys, remember that a 8-core ccx doesn't necessarily means all 8 cores active in the same ccx in all sku's. Regardless of nm process, they will probably release variants of 3+3, 6+0, 4+4, 8+0, etc, which increase yields tremendously and keeps lower tiers cheap.
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Is there going to be a higher max clock speed on the infinity fabric this time? The Zen 2 limit was a pain, and meant my expensive DDR4 RAM could not be run as fast as it should have been, and actually the particular silicon lottery 3900X chip I got did not even clock to the AMD recommended infinity fabric clock speed (1800MHz for 3600MHZ RAM) - mine was only stable up to about 1700MHz.
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Ricardo:

Guys, remember that a 8-core ccx doesn't necessarily means all 8 cores active in the same ccx in all sku's.
the whole point of the 8 core ccx is to not use another for more cores, removing the penalty of ccx<>ccx communications.
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I personally don't think this will turn out to be true even if It would be awesome if it was true. AMD would have already needed to be working on this a few months ago and the timing seems a bit risky. I will be pleasantly surprised if this turns out to be true but i'm very skeptical. 8-core CCX - This one is easy and obvious evolution. For gaming and low power laptop chips you get better performance and power. This latency reduction is needed to attack Intel in the very high FPS category. The infinity fabric consumes a decent amount of power so we should see 6 and 8 core Zen3 based laptop APU's with lower power needs. I doubt we will see AMD increase over 8-core CCX's as its already been shown you start to have latency issues when having over 8-cores on a ring bus which each CCX has something akin to Intels ring bus to link all the cores.
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Ricardo:

Guys, remember that a 8-core ccx doesn't necessarily means all 8 cores active in the same ccx in all sku's.
That is true, but it's important to consider what an 8-core CCX means in terms of binned parts: A fully-functional die could make a 4800X, or a pair could make 4950X (assuming core counts are the same for next-gen). A die with 6 working cores could make a 4600X, or a pair could make a 4920X. A die with 4 working cores could make a 4300X, or a pair could make a 4700. A die with 3 working cores could make a decent low-end mobile platform, or a pair could make a 4600. A pair of 2-core dies could make a 4100. Meanwhile, there's now the option for 7 and 5 core variants, which weren't possible before. That means the 4900X could be a 10c/20t model and there could be a 4940X for a 14c/28t model. EDIT: Somehow I forgot to mention: my proposed ideas for the 4800X, 4600X, and 4300X would allow for some major performance improvements over the 4700, 4600, and 4100. So even though we're seeing relatively low-core parts, there will actually be a compelling reason to buy these X variants, which was never the case before.
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Astyanax:

the whole point of the 8 core ccx is to not use another for more cores, removing the penalty of ccx<>ccx communications.
Yes, that's why I pointed both cases: a more high end 6+0 or 8+0 SKU, and a budget one using two ccx's in 3+3, 4+4, 4+2, etc. CCX penalty is not that high, Zen 2 is already pretty fast even with that factor.
schmidtbag:

That is true, but it's important to consider what an 8-core CCX means in terms of binned parts: A fully-functional die could make a 4800X, or a pair could make 4950X (assuming core counts are the same for next-gen). A die with 6 working cores could make a 4600X, or a pair could make a 4920X. A die with 4 working cores could make a 4300X, or a pair could make a 4700. A die with 3 working cores could make a decent low-end mobile platform, or a pair could make a 4600. A pair of 2-core dies could make a 4100. Meanwhile, there's now the option for 7 and 5 core variants, which weren't possible before. That means the 4900X could be a 10c/20t model and there could be a 4940X for a 14c/28t model.
That is precisely my point: more cores per CCX's means more options for SKUs and thus better cost efficiency on manufacturing these chips. That could be a pretty strong reason to just go directly into 5nm a bit later - to fit those 8 cores easier.
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Well considering the rumors of 3x00XT processors, it all makes sense now. I don't mind waiting a little longer. But I guess only time will tell.
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Well damn, and I was pretty confident that I'll stick with my 3900X and skip the 4000 series. But if these come out in spring next year then the upgrade won't sound so bad, as by that time I'd be having the 3900X for over 1.5 years. It makes sense though, ever since those XT CPUs rumors, I thought it unlikely that both will launch in the same year. I just hope my X570 Aorus Master will handle these, cause if I need to change the mobo, I'll definitely pass.
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Ricardo:

Yes, that's why I pointed both cases: a more high end 6+0 or 8+0 SKU, and a budget one using two ccx's in 3+3, 4+4, 4+2, etc. CCX penalty is not that high, Zen 2 is already pretty fast even with that factor. That is precisely my point: more cores per CCX's means more options for SKUs and thus better cost efficiency on manufacturing these chips. That could be a pretty strong reason to just go directly into 5nm a bit later - to fit those 8 cores easier.
I hope that you noticed that Zen2 CPU chiplet (CCD) consists of two CCXes. Therefore Chiplet itself has 8 cores/16 threads. Idea here is that Zen3 CPU chiplet CCD=CCX, in other words, nothing changes in terms of available cores per chiplet. But it changes for X+Y cores per CPU socket. Now you have 2+2 or 4+0 within one Chiplet. That means 2 cores in 1st CCX and two cores in 2nd CCX within one CCD. Or 4 cores in one CCX (Full) + 0 cores in 2nd CCX (dead). In case of 8 cores per CCX, it would still be 4 core out of 8 enabled regardless of their position within CCX because there is just one CCX. To have 2+2 configuration one would have to put 2 CCDs (2 separate chiplets) on interposer like with 3900X/3950X. Except that 3900X is 3+3 & 3+3 where CCX0 has 3 cores, CCX1 has 3 cores and they together form CCD0. Then there is CCX2 with 3 cores and CCX3 with 3 cores which together form CCD1. And then they are connected via IF. Zen 2 way is having increased latency within CCD if there is movement of data between CCXes adn additional latency in case CCX in one CCD moves data to CCX in other CCD. Zen 3 practically kills off CCX to CCX communication latency within one CCD as all cores are part of same CCX. - - - - Would AMD scrap 2 chiplets with just 2 live cores out of 8 to form CPU that has 2 CPU chiplets in 2+2 configuration with Zen3? Well, if it is worth putting one almost dead chiplet on interposer, it surely is worth putting two of them there. But question is actual volume of such low quality chips. If we looked back on how high were initial yields for Zen2, it would be clear that 6 dead out of 8 cores would be rare situation. As far as CCX penalty goes, you can check clock to clock comparison of 3100 vs 3300X. If AMD takes the road like 6 cores in one CCX=CCD vs 3+3 cores in 2 separate CCDs (Chiplets), they should clearly indicate it in naming scheme as there is difference. Because later will have worse performance while sipping more power at same clock. (Maybe 3+3 would end up being cooler and able to clock higher, but it would still be worse at comparable clock and be less power efficient.)
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Ricardo:

CCX penalty is not that high, Zen 2 is already pretty fast even with that factor.
its still a measurable performance reducer in single process all core applications.
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Venix:

Depending how big the chiplets will end up assuming they will keep the same amount of chiplets on each category that would mean up to 32 cores for mainstream and up to 128 for hedt if they indeed move to 8 core ccx dunno 32 core sound unlikely on the other hand when ryzen 1 released i do not think many expected 16 core on the next arch not before the first delided cpu lisa showed of zen 2 so we will see , or they might do 24 core to maximize yields and drop 32 on zen 3+
You guys are getting it wrong. They're doubling the number of cores per CCX, not the total amount of cores. It even appeared on a roadmap slide for EPYC (I mean, it was released last year so still subject to change, but Milan is supposed to still be 64 cores per socket). This change in CCX layout is to improve some latency in cases where there's cross-CCX data exchange, and it goes hand-in-hand with the changes they're making to the L3 cache (making the whole block available to the entire CCX, instead of dividing it like now). It's a IPC-focused move, not throughput. Basically instead of having 2 CCX per chiplet we'll have 1, albeit more integrated.
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Astyanax:

its still a measurable performance reducer in single process all core applications.
You wrote that understatement rather nicely. Difference in performance between 2+2 in one CCD and 4+0 in 1 CCD is rather high. Would it be 4 in just one CCD vs 2+2 in two CCDs, difference is likely going to be even better. Data are available all over net. I am sure you know it well. So this is for those who are interested but did not look for it, yet. [youtube=NM2fFpzPKPg] Timestamp link to part where interesting information starts.
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I suspect with the 3100 vs 3300, theres actually a memory throughput disadvantage on the 3100 that causes it to suffer in gaming tests
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I'll believe it when I see it. Remember the 5Ghz rumours. 😀