New AMD Threadripper chipsets pop up in USB-IF database - No more X599 ?

Published 2019-08-29 13:17 by Hilbert Hagedoorn

Click here to post a comment for New AMD Threadripper chipsets pop up in USB-IF database - No more X599 ? on our message forum

#5705469

Devid

2019-08-29 13:53

TRX40@4 channel memory upto 32 cores TRX80@8 channel memory upto 64 cores WRX80@8 channel memory upto 64 cores as this is a workstation stuff. I could bet on these 😉 All this means TR3 platform will be a real killer 🙂

#5705492

anticupidon

2019-08-29 14:18

Hope until then Microsoft developers will tweak the Windows scheduler to properly make use of those cores. For those who don't know about it, here it is. [youtube=M2LOMTpCtLA]

#5705516

schmidtbag

2019-08-29 15:09

anticupidon:

Hope until then Microsoft developers will tweak the Windows scheduler to properly make use of those cores. For those who don't know about it, here it is. [youtube=M2LOMTpCtLA]

Well, if the Threadripper 3000 series ends up being based on chiplets, the Windows scheduler (although still incompetent) isn't going to result in such drastically terrible results without being modified. The chiplet design is substantially more tolerant of schedulers that like to [needlessly] swap tasks between different cores (which is the barebone reason why the 2990WX performed so poorly). MS still needs to fix this behavior, but, at least the performance shouldn't be so bad that someone like Wendel needs to spend so much time investigating a solution. Anyway, as a BOINC user, I sure am going to be excited when all those 2990WXs sell for dirt cheap because of how tremendously obsolete they'll become, even though they're actually super capable CPUs under the right conditions.

#5705544

Fox2232

2019-08-29 15:50

Can someone imagine storage made entirely of 8GB HBM chips backed by battery connected via PCIe 4.0 x32?

#5705550

schmidtbag

2019-08-29 16:00

Fox2232:

Can someone imagine storage made entirely of 8GB HBM chips backed by battery connected via PCIe 4.0 x32?

https://en.wikipedia.org/wiki/Resistive_random-access_memory It's not HBM but being non-volatile on a system with 4-8 memory controllers (and in turn, direct CPU access, rather than communication over PCIe), I think I'd rather opt for that. I dream of a day where ReRAM becomes affordable, and obsoletes the need of both disk storage and RAM as we know it. There would be no such thing as loading; the CPU just reads/writes directly from the source as needed, and only whatever is needed. No more lost data from power outages. No need for suspend/hibernate. No point in caching/buffering.

#5705556

Fox2232

2019-08-29 16:08

schmidtbag:

https://en.wikipedia.org/wiki/Resistive_random-access_memory It's not HBM but being non-volatile on a system with 4-8 memory controllers (and in turn, direct CPU access, rather than communication over PCIe), I think I'd rather opt for that. I dream of a day where ReRAM becomes affordable, and obsoletes the need of both disk storage and RAM as we know it. There would be no such thing as loading; the CPU just reads/writes directly from the source as needed, and only whatever is needed. No more lost data from power outages. No need for suspend/hibernate. No point in caching/buffering.

Yes. But it has that issue called system reliability in general. On finely tuned linux workstation, it would be great. With buggy windows and need to restart with updates... Half of benefits lost. I think we sooner get PCIe 5.0 and M.2 NVMe drives reading 10GB/s+. What I meant was sheer amount of bandwidth available via given interface. And HBM could even be downclocked for "power efficiency" as it would be still overkill. And compete with RAM itself in terms of bandwidth.

#5705611

nizzen

2019-08-29 18:01

What I want for storage: Lower latency > higher bandwidt Ps, I running a Intel Optane 900p with my Ryzen 3900x 🙂

#5705654

holystarlight

2019-08-29 19:36

I love how AMD still keeping same sockets for these new threadripper line, im excited to upgrade!

#5705675

Evildead666

2019-08-29 20:56

I wonder if we'll see the fabled X590 ? I could imagine a really bad TR I/O chip being reused as an AM4 chipset just for the extra PCIe lanes. TDP might be a problem tho. Fan almost guaranteed.

#5705678