Fediuld:

Thought when they were moving away from the Sky-lake architecture it won't be named "*-Lake" any more?

Yosif Videlov:

And by the time they release the 7nm, AMD will be at 5nm already and going for the 3nm process. 🙂

Yosif Videlov:

And by the time they release the 7nm, AMD will be at 5nm already and going for the 3nm process. 🙂

Denial:

The numbers are pretty meaningless when the feature sizes are nearly identical. The industry really needs to move away from those numbers - it's extremely misleading. For example the Gate Pitch of 7nm is actually 54nm. Intel's 10nm process in some ways is more dense than TSMC's 7nm process.

D1stRU3T0R:

So why they use it? Is that the smallest process that's in there? It's like producing a car with 500hp, but calling it Ford Mustang 700HP

Roughly for the first 35 years of the semiconductor history, since the first mass production of MOSFET in the 1960s to the late 1990s, the process node more or less referred to the transistor's gate length (Lg) which was also considered the "minimum feature size". For example, Intel's 0.5 µm process had Lg = 0.5 µm. This lasted until the 0.25 µm process in 1997 at which point Intel started introducing more aggressive gate length scaling. For example, their 0.25 µm process had Lg = 0.20 µm and likewise, their 0.18 µm process had Lg = 0.13 µm (a node ahead). At those nodes the "process node" was effectively larger than the gate length. The ITRS traditionally defined the process node as the smallest half-pitch of contacted metal 1 lines allowed in the fabrication process. It is a common metric used to describe and differentiate the technologies used in fabricating integrated circuits. Meaning lost At the 45 nm process, Intel reached a gate length of 25 nm on a traditional planar transistor. At that node the gate length scaling effectively stalled; any further scaling to the gate length would produce less desirable results. Following the 32 nm process node, while other aspects of the transistor shrunk, the gate length was actually increased. With the introduction of FinFET by Intel in their 22 nm process, the transistor density continued to increase all while the gate length remained more or less a constant. This is due to the properties of FinFET; for example the effective channel length is a function of the new fins (Weff = 2 * Hfin + Wfin). Due to how the transistor changed dramatically from how it used to be, the current naming scheme lost any meaning.

D1stRU3T0R:

So why they use it? Is that the smallest process that's in there? It's like producing a car with 500hp, but calling it Ford Mustang 700HP

SoLoR:

crashing like a meteor? imagine all the memes...

yeeeeman:

AMD will use 7nm for Zen 3, that will launch end of this year or start of next year, so 2021. In 2022 Zen 4 on 5nm will launch. In 2022, Intel should also have a 7nm product. Its not all about process, but it does bring a significant benefit in terms of efficiency.

JamesSneed:

It's not all about process but it will be at some point when you can make something on the new process the competitor can't.

JamesSneed:

Whoever can first get to densities that allow APU's to have 8-cores, 32+GB HBM2 and 2080 ti level GPU on die without needing exhotic cooling will have the first real gaming APU's. Whoever gets there first will take the market by storm. Of course process is a huge part but making in house HBM to keep costs low and also 3d stacking will come into play. It's not far off since the next gen console chips are already pretty close to this performance.

ToxicTaZ:

More like if AMD was the Dinosaurs and Intel Meteor Lake is coming lol

Noisiv:

SoLoR:

hehe funny but totally wrong right now, considering amd is a hot new thing and intel is 14nm dinosaur for last what ? 5-6 years? If anyone is dinosaur its intel ;P