I wonder how it compares to the way TSMC and Intel define a nanometer.
Seems like it would be similar to a 3nm enhanced node that I'm sure TSMC is working on. Difference is TSMC is probably already running pilots of 3nm while this is still in the lab. Will be useful to other foundries/competition though.
Seems like it would be similar to a 3nm enhanced node that I'm sure TSMC is working on. Difference is TSMC is probably already running pilots of 3nm while this is still in the lab. Will be useful to other foundries/competition though.
We need a better naming scheme, like "transistor density per mm2" for example. The nm naming scheme is a big marketing bs.
We need a better naming scheme, like "transistor density per mm2" for example. The nm naming scheme is a big marketing bs.
This 1000 times .i think the last time we had real nm naming was on 20nm pre finfet that was more expensive had smaller yields and offered almost no advantages over the 28nm proccess so nobody touched it. Later what became 16 nm for tsmc and 14nm for glofo was actually 20nm finfet it was so much better than the traditional 20nm they decided to market it like that ..... And the rest is history. They just kept going like that
schmidtbag:
I've said the same thing. Though, that's going to get complicated whenever we see Foveros chips show up.
Seems like it would be similar to a 3nm enhanced node that I'm sure TSMC is working on. Difference is TSMC is probably already running pilots of 3nm while this is still in the lab. Will be useful to other foundries/competition though.