GeForce GTX 1180 PCB Leaked

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#5570377
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😱
#5570382
https://forums.guru3d.com/data/avatars/m/80/80129.jpg
That GPU size looks really small.. like ~350mm2 small.. I don't really know what to make of that.
#5570384
https://forums.guru3d.com/data/avatars/m/215/215813.jpg
So it has 6 pin + 8 pin power connectors and SLI capability
#5570386
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Denial:

That GPU size looks really small.. like ~350mm2 small.. I don't really know what to make of that.
But you have 8 times GDDR?6?! One can only wonder, 6+8 pin. And power delivery seems rather solid. Even on "12nm" that can mean 200/100MHz boost on min/max, maybe more on min if power draw is to be bit higher.
#5570390
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Nvlink is connecting 2 cards as one. 8+8 GB memory is 16GB, and 5000+5000 cudacores is 10 000 cudacores 😀
#5570392
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nizzen:

Nvlink is connecting 2 cards as one. 8+8 GB memory is 16GB, and 5000+5000 cudacores is 10 000 cudacores 😀
That is always true. cuda cores are always doubled, i have difficulties to believe that for how much smart that connector can be, one gpu can retrieve a texture from the other card and allowing effective full memory usage of 2 cards.... Especially if is also used to move the framebuffer from one card to the other. I'm sceptical but cannot wait for some news/ article.
#5570393
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The Nvlink connector is reversed to the Titan V as in the bridge would probably have to be upside down, either the 11 series will have an entirely different Nvlink bridge or this is an early development board. It might make sense having a different Nvlink standard for gaming GPU's due to the fact the current bridge on the market costs more than a 1080.
#5570394
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asturur:

That is always true. cuda cores are always doubled, i have difficulties to believe that for how much smart that connector can be, one gpu can retrieve a texture from the other card and allowing effective full memory usage of 2 cards.... Especially if is also used to move the framebuffer from one card to the other. I'm sceptical but cannot wait for some news/ article.
Take nVLink bandwidth. Imagine 1/2 of data read at 360GB/s and then 1/2 at 50GB/s from other card. Count time to read it if Each card has 6GB cloned (360GB/s) and 1 GB shared (50GB/s). In server compute, this is not an issue. Especially since there are multiple channels and bandwidth can go up.
#5570398
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Denial:

That GPU size looks really small.. like ~350mm2 small.. I don't really know what to make of that.
Really interesting indeed. I'm not sure this means it's not the PCB for the 1180 itself due to the chip size, or Nvidia did the unbelievable and did a node shrink nobody knew about... which I can't really imagine. So if that is an NVlink connector... does that mean we get pooled resources, and that it easens mGPU adoption for developers, because they don't have to adress two cards but only the "GPU pool"?
#5570403
https://forums.guru3d.com/data/avatars/m/269/269303.jpg
Oooh it's starting to get tasty
#5570406
https://forums.guru3d.com/data/avatars/m/115/115462.jpg
If this is 16GB, I'm really curious what the 1180Ti will have... 😱
#5570408
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Denial:

That GPU size looks really small.. like ~350mm2 small.. I don't really know what to make of that.
Looking at the image and measuring the size of the PCI-E connector vs the size of the solder pad area and using this information to scale the pad area to its approximate size I get a rough chip package size of at least 4.75 centimeters square. I haven't been able to find a bare PCB shot of a GTX 1080 board, but I did find an image from Chiphell where they measured the chip package of a GP104 chip which came to around 3.75 cm square. This means that the chip itself is has an area that is at least 60% larger. What this means for the die itself is unclear, but since the process has shrunk to 12nm vs 16 nm for Pascal, we have to assume that a bigger die together with a smaller process would mean a lot more transistors!
#5570410
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Let's hope for a decent jump in performance, they had plenty of time for refinements
#5570412
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It's all about how much better than Pascal this is. If this really is 12nm, then, that almost guarantees a refresh next year on 7nm as well.
#5570413
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Stormyandcold:

It's all about how much better than Pascal this is. If this really is 12nm, then, that almost guarantees a refresh next year on 7nm as well.
a 7nm product wouldn't be a refresh. its a new node. 12nm is just marketing name for the refined 16nm that Pascal is using.
#5570414
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Crazy Joe:

Looking at the image and measuring the size of the PCI-E connector vs the size of the solder pad area and using this information to scale the pad area to its approximate size I get a rough chip package size of at least 4.75 centimeters square. I haven't been able to find a bare PCB shot of a GTX 1080 board, but I did find an image from Chiphell where they measured the chip package of a GP104 chip which came to around 3.75 cm square. This means that the chip itself is has an area that is at least 60% larger. What this means for the die itself is unclear, but since the process has shrunk to 12nm vs 16 nm for Pascal, we have to assume that a bigger die together with a smaller process would mean a lot more transistors!
#theydidthemath If that's the case it's bigger than my first glance. I guess it depends on what library they are using - TSMC has a 6T available with a 20% reduction in density but AFAIK it's only optimized for low power. The Titan V uses 7.5T with no density improvement but I also don't know the specifics of Nvidia's custom FFN process, it's possible that this chip will be fabbed on some variant of that. Anandtech has a handy little chart here: https://i.imgur.com/wTYQwb4.png
#5570419
https://forums.guru3d.com/data/avatars/m/122/122801.jpg
Yeah, take these 1080TI n toss them no one wants them. We made too much off them so............I find it hard to believe!
#5570422
https://forums.guru3d.com/data/avatars/m/273/273678.jpg
asturur:

That is always true. cuda cores are always doubled, i have difficulties to believe that for how much smart that connector can be, one gpu can retrieve a texture from the other card and allowing effective full memory usage of 2 cards.... Especially if is also used to move the framebuffer from one card to the other. I'm sceptical but cannot wait for some news/ article.
3DFX did it back in the day, if the memory interface is a multi-port ring bus theres no reason that near full speed access can't be achieved across the nvlink.
#5570432
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HardwareCaps:

a 7nm product wouldn't be a refresh. its a new node. 12nm is just marketing name for the refined 16nm that Pascal is using.
That only depends on how TSMC realizes the 7nm...

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