AMD ZEN2 Rome Listed in Sandra, shows doubled up L3 caches
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Fox2232
Maybe that can explain hugeness of that central die.
asturur
oh do you think all the cache is there?
Fox2232
It is L3. That definitely does not need to be locally present in chiplets. L1 must be inside CPU chiplet. L2 is likely better off in CPU chiplet too. But L3, maybe having it in big Chip may allow for some extra optimizations.
asturur
well if the infinity fabric is used to fetch from l3 to l2 and that IO thing fetch from memory to l3, i can see how you should not have efficency hit.
Also use the 7 nanometers process to do cores and not memory.
On a separate topic i wonder if they can transition to more memory channel without changing them motherboard, assuming the controller for memory is in the package and not in the MB this could be eventually possible.
Is just a curiosity because we know this change is out of scope for various reasons. I m just wondering if it would be techincally possible
nevcairiel
Well, you have to change the motherboard, thats no question. Every memory channel is connected to the CPU, while slots on the same channel are connected differently. The real question is if they can do it without a new socket - and that depends if it was pre-planned and/or enough reserved pins are available.
Aura89
This news item is for servers, of which states 8-channel support, of which current 1st gen Epyc processors already support 8-channel memory.
If this goes over to threadripper as 8-channel capable, we'll see, but i doubt it, there's not a huge reason to. But considering Epyc and Threadripper use effectively the same socket/pins, there's also likely nothing "stopping" them from supporting it if they wanted.
But i very much doubt that 8-channel is coming to threadripper, or 4-channel is going to Ryzen.
Astyanax
There is, the fact the x399 socket is wired to have 8 dimms connected to 4 controllers instead of 8 dimms wired to 8 controllers.
Aura89
Redundancies in systems that would allow a CPU to work in 8-channel or 4-channel based off the motherboard chipset it is in considering that socket is used for both 4-channel and 8-channel is information we do not know about.
I didn't say it wouldn't require a new motherboard chipset, obviously if they brought 8-channel memory support to threadripper, it would be via a different chipset, but that doesn't mean it wouldn't still be backwards compatible with previous chipsets for 4-channel.
But again, i do not believe that will happen. I see no reason as to why they would change from Ryzen being dual, Threadripper being quad, and Epyc being 8-channel.
AlmondMan
Double up on cache, double up on cores? Seems they found a way to glue CCXs together too!
asturur
This i did not know.
I thought that since the memory controller is moved in the cpu, each dimm socket would go to the cpu and that the 2/4 channel would have been something internal wiring to the memory controller. ( the mb chipset do not play a role in the configuration, i m sure )
It was a generic question not related to ryzen or threadripper or Epyc in particular.
schmidtbag
Did you mean chiplets?
'member when L2 caches used to be wholly separate from the CPU package?
Petr V
I cant wait to see Zen 2 official review.
Will be intresting how much cores new top model will have.
12 core 3700X can be alright.
Ridiric
I 'member that!
Alessio1989
Zen 2 threads are becoming an hard-porn video collections.
D3M1G0D
I've heard speculation that the cache in the IO die might contain a copy of the cache for each chiplet, which would negate the need for chiplet-to-chiplet communication.
ManofGod
The hype itself is not coming from AMD themselves. They appeared to have learned not to hype their own product themselves.
