On the eve of the annual TSMC Technology Symposium on April 7, Cadence sat down with Suk Lee, Senior Director, Design Infrastructure Marketing Division of TSMC (pictured nearby), to get his sense for trends and challenges facing the electronics design ecosystem.
Q: Mark Liu (TSMC president and co-CEO) indicated at OIP last fall that 10nm is a fast-rising node, right behind 16nm. Where do we stand with 10nm development? Do you still expect customer tapeouts in the second half of 2015?
Lee: Our 10nm is progressing. We have completed certification of over 35 EDA tools using ARM's CPU core as the vehicle. In addition, we have started the IP validation process six months earlier than previous nodes with our IP partners. We are working with over 10 customers on their 10nm product design. The qualification schedule remains at the end of 2015. We are working with customers on tapeout, and we expect volume production in 2017.
Q: Can you share any insights on 7nm development?
Lee: I don't want to make any comment on a specific technology node number but we're working on future platform technology development. We have a team working on the next generation after 10nm. Those technologies are going to be offered in the 2017 to 2019 period. We don't anticipate Moore's Law is going to slow down anytime soon.
Q: Engineers apply lessons of any process node ramp to the subsequent process. What did 16nm learn from 20 and what is 10nm learning from 16?
Lee: The blogosphere about two years ago had some commentary about "wow 20 v. FinFET--that seems like a mistake." We had a conscious strategy, which was creating the ultimate planar technology with 20nm SoC and then spinning out 16nm FinFET with essentially the same metal stack. That was a great risk mitigation strategy for TSMC. We had a very advanced metal stack with a set of leading customers who wanted to squeeze every last drop out of planar. So 20nm turned into a great deal of business for us. We didn't have to take on two challenges at the same time—developing this complex metal system and bringing up FinFET. We've enjoyed the manufacturing learnings on the metal system, and that has made the ramp on 16FF much easier. You've seen in the press some of our competitors are struggling with their FinFET technology yields. Our technology has moved forward very smoothly.
Q: So how about from 16 to 10nm?
Lee: The thing that carries forward from 16 to 10nm is basic FinFET learning obviously, but also the techniques that we've refined on 16nm to handle multiple patterning segue smoothly into 10nm.
In general, one of the things we've done in the past four years is that we've engaged with the EDA/IP ecosystems earlier and earlier. We used to engage at SPICE 1.0. The pace of technology development and the pace of our customers' product cycles means that we've had to engage much earlier than in the past. For the ecosystem, one of the things that started at 28 and came to full fruition at 16 was that we mutually learned how to do process and full product all in parallel. That's really going to be a critical thing for 10. We're working with the ecosystem on 10. Our customers already are working on 10nm product designs. That's the result of the learning that we applied with the ecosystem on 28, 20, and 16 on how to do concurrent ecosystem and process bring up. That's enabled us to engage very quickly at 10nm.
Q: There’s been talk that the FinFET era will be a short one, perhaps only two or three nodes. Is that the case? If so, what’s next? If that’s not the case, how are we stretching out FinFET’s usefulness?
Lee: From 16 to 10nm to the next generation we’ve still got a number of years ahead of us. People thought that 20 wasn't going to be such a big runner because 28 was so popular. If you look at volumes on 28, 20, and now 16, it's reasonable to expect that volumes and production cycles on 10 and so forth are such that this is going to be a significant era for design-ins and production volumes.