Long time untill we see GPU's saturate PCIE4.0 , but for storage it is different story i hear .

kapu:

Long time untill we see GPU's saturate PCIE4.0 , but for storage it is different story i hear .

I does not look like there is enough marked for fast storrage outside enterprise use. It is possible to buy a PCI Express 3.0 x8 lane SSD card with essentially the same speed (6.5GB/s) as a 4.0 x4 lane SSD (7GB/s), so a 4.0 x16 lane SSD with 28GB/s should not be a problem, but it does not look like there is a marked for it.

About time, we're getting bored of PCIE 5.0!

:)))

Mufflore:

About time, we're getting bored of PCIE 5.0!

Cant wait for the reviews that show that in real world scenario's like gaming....it makes very little change

The Goose:

Cant wait for the reviews that show that in real world scenario's like gaming....it makes very little change

That's why I've been saying for a while now that we should just ditch the x16 slot. But many others here seem to vehemently disagree with me on this. As bus speeds go up, so does the complexity and cost of the motherboards. It makes more sense to have fewer+faster lanes than it does to have a few big lanes. Even in the server world, a lot of cards are x8. I thing PCIe 6.0 is the perfect time to ditch the x16 slot, since there currently is no use for so much bandwidth per-lane. By the time such bandwidth is necessary, PCIe 7.0 could likely be achieved.

Mufflore:

About time, we're getting bored of PCIE 5.0!

Just waiting for them to announce PCIE 7.0 before there are any PCIE 6.0 cards on the market 😉

Falkentyne:

Just waiting for them to announce PCIE 7.0 before there are any PCIE 6.0 cards on the market 😉

I will not be surprised if geforce 4xxx and radeon 7xxx are still on pcie 4 if i am honest.

schmidtbag:

That's why I've been saying for a while now that we should just ditch the x16 slot. But many others here seem to vehemently disagree with me on this. As bus speeds go up, so does the complexity and cost of the motherboards. It makes more sense to have fewer+faster lanes than it does to have a few big lanes. Even in the server world, a lot of cards are x8. I thing PCIe 6.0 is the perfect time to ditch the x16 slot, since there currently is no use for so much bandwidth per-lane. By the time such bandwidth is necessary, PCIe 7.0 could likely be achieved.

Why ditch it? if a GPU cannot do x16 it just changes to x8 mode anyway so it does that for us. Rather we kept the slots even if they go to x8/4 I'd rather they look into a way to run at x12 if I am honest so open more lanes though with pcie 5 out i doubt we will get bottlenecked for awhile

Ricepudding:

Why ditch it? if a GPU cannot do x16 it just changes to x8 mode anyway so it does that for us. Rather we kept the slots even if they go to x8/4 I'd rather they look into a way to run at x12 if I am honest so open more lanes though with pcie 5 out i doubt we will get bottlenecked for awhile

As I said, the problem is the motherboard. The faster the bandwidth gets, the more sensitive it gets to data corruption. The more lanes you have, the more of a risk EMI will cause such corruption. In order to accommodate those extra lanes, motherboard designs become more complex and more expensive. Keeping x16 slots is a lose-lose situation going forward. They were necessary in the PCIe 1.0 and 2.0/2.1 days because technology was evolving rapidly and engineers needed a way to make sure backward compatibility wasn't a bottleneck. For PCIe 3.0, it took several years for x8 slots to get saturated, but it made sense to include x16 because of 1.0 and 2.x cards x16 cards that would run slower. The thing is, PCIe 4.0 came out a tad too late. If it were released in maybe 2015, they could have ditched x16 slots without any detriment to performance of practically anything, and it would have been easier to approach back then because like I said: it's less complicated electrically to have fewer lanes. I'd say 2017 is around when x8 4.0 lanes would have been saturated, so, that would have been a good time to release PCIe 5.0, which as you said, won't get bottlenecked for a while.

schmidtbag:

As I said, the problem is the motherboard. The faster the bandwidth gets, the more sensitive it gets to data corruption. The more lanes you have, the more of a risk EMI will cause such corruption. In order to accommodate those extra lanes, motherboard designs become more complex and more expensive.

As far as I understand routing 5.0 8 lanes is more sensitive then routing 4.0 16 lanes, because 5.0 is higher frequency and speed per lane and per individual motherboard trace. Routing 4 lanes of 6.0 would be more demanding on the mainboard, then routing 16 lanes of 4.0 and the end speed would be the same. The full size PCI X slot is still needed to physically support the heavy cards, so the slot itself can not be sized down, so it might aswell be fully populated if it is physically there anyway.

TLD LARS:

As far as I understand routing 5.0 8 lanes is more sensitive then routing 4.0 16 lanes, because 5.0 is higher frequency and speed per lane and per individual motherboard trace.

Right, all the more reason to ditch x16 slots.

The full size PCI X slot is still needed to physically support the heavy cards, so the slot itself can not be sized down, so it might aswell be fully populated if it is physically there anyway.

Yeah that had occurred to me. Honestly, I think there needs to be a new motherboard standard for mounting such large expansion cards, because even the x16 slot isn't strong enough in some cases.

schmidtbag:

Right, all the more reason to ditch x16 slots.

no, just more reason to ditch NRZ for PAM4

kapu:

Long time untill we see GPU's saturate PCIE4.0 , but for storage it is different story i hear .

This is for the enterprise first. They have been salivating at getting faster PCIe for quite a few years. They need very high data rates for 800Gb/s networks or faster, Artificial Intelligence/Machine Learning, and HPC. I like that its enterprise first well ahead of consumer needs as at least the standard/option exists before its needed unlike prior decades the client/PC side always had a use case that was PCIe/PCI/ISA constrained before the new standard was out.