Next-gen AMD EPYC (Genoa) Would get 50% larger socket SP5, 96 cores and 400W TDP
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Fox2232
I get that when server has 50% more cores, it can benefit from 50% higher memory bandwidth.
But was not DDR5 supposed to deliver higher bandwidth by itself?
What would be speculated use of 12 memory channels + extra bandwidth per channel? (Conspiracy theory about drastic increase in Zen4 IPC or EPYC all core boost clock.)
Evildead666
Extra bandwidth available from PCIE5 devices would be my idea.
PCIE4 was pretty power hungry compared to PCIE3, and PCIE5 will be no different.
High frequencies will require more power for the moment, until it gets optimized, and maybe a lithography shrink (if that helps).
I was more expecting the CCX's to go to 12 cores rather than the extra chiplets.
Then again, with the increase in pin count, and overall 'chip' size, they would have the room.
12 memory channels/PCIE5 would mean a new IO die as well.
Bitey
more cores means the requirement for more independent mermory channels goes up for latency reasons and a new socket has to have the legs for quite a few years so a bit overkill now is barely adequate when the socket dies
bnauk
400W? So, matching the next gen 8 core Intel desktop CPU then. This is fine
Undying
It will support AVX3-512 instructions.
Fediuld
Yep with a 96 core CPU 😀
marashz
And Intel only with 8 core 😀
Robson
No, it's not mainboard it's a socket. 😱
I never understand why DDR5 is coming, DDR6 has been for years.
kakiharaFRS
I've seen what 400W on a cpu does with an oc threadripper, it's unusable unless it's in an air-conditioned room, which ok it's a server part but just saying
I had 38°C ambient temp at the end of my overclocking shenanigans 😱
Alessio1989
Except that on server side, usually the CPUs respect the TDP as maximum power.
TLD LARS
400W Epic is still a lot less heat then a 4 socket full of 24 core Xeons with maybe a TDP of 800-1000W instead, to be able to keep op with this monster.
The reason for the needed 12 channel memory previous mentioned, could be because DDR 5 needs to be 4500 or something like that, to beat a good DDR4 3200 kit.
Every memory jump until now have had overlapping performance, next generation mostly needs multible months with new module releases, before they begin to perform faster then last generation.
386SX
12 channel memory.
96 cores / 192 threads
160 pcie lanes
400W TDP ....
... in one single package.
I would like to see Noctua to build an air cooler for that. 😀
Neo Cyrus
400W for 96 of those cores is nothing. As a server chip of course they have to go for very good performance per watt since that's a key selling point, but I just like thinking about what kind of monster chips they could design if they went for just raw power, the limit before a big falloff / massively diminishing returns. You'd still probably not need one of those industrial chillers which Intel uses to lie to the public about their products.
Btw Intel, how go your server chips?
Nero1024
I think you have misstaken GDDR6 for DDR6, they are not the same
nosirrahx
64/8 = 96/12
Mundosold
the heatsink would be so big it would double as the case, and you would use a Noctua brand Walmart-style $20 box fan with it (colored mocha/tan as always)
Fox2232
Yeah. And? Like that would be part of one sentence I wrote. And Ignoring the rest.
One DDR5 has much higher bandwidth by itself than One DDR4.
When you increase number of memory banks by 50%, and bandwidth each memory bank provides by 40%. How much more bandwidth you get?
And you are getting this increase while adding only 50% more cores.
So, either AMD is future proofing socket a lot. Or Zen4 can actually process data quite faster than Zen3.
JamesSneed
The first chips of the next generation of DDR usually are not much improvement if any at all. Sure the frequency is higher but the latency is as well so realized bandwidth doesn't move much. This is why I never get excited about a new DDR generation a least not the first iteration. In 2-3 years DDR5 will far surpass DDR4 but that will not be the case at first.
Fox2232
You wrote a lot. And you are not wrong. But ignored elephant in the room I was pointing on entire time.
Do you have estimation on initial available bandwidth change from SP4 to SP5 socket CPU per core, when we say that SP4 has top chip with 64 cores and SP5 has top chip with 96 cores?
No need to write bandwidths. Just multiplier, percentage or ratio will be enough.
And do you have estimation on this change in 2~3 years when DDR5 mature?
nosirrahx
They are not going to reduce the number of channels per core, even from just a marketing standpoint.
Software over time becomes more and more hungry for memory (both capacity and throughput), this is not a static metric.
You are also operating under the assumption that DDR4 100% meets the needs of the existing processors, that adding frequency would have 0 impact, which clearly isn't true.
