I heared a rumor that Ryzen2 7Nm will bring 12 to 16 core to the AM4 platform, and gets a 10 to 15% IPC gain over Ryzen 2000 series on 12Nm.

There are a ton of rumors flying around right now about AMD's Zen 2. I really don't see AMD introducing a design risk like changing the CCX size for Zen 2. As a company moving down a full node from 14nm to 7nm you simply wouldn't introduce anymore risk than needed. I would expect some IPC improvements(< 10%) and much higher clocks like in the 20% range. The IBM developed 7nm process should hit much higher frequencies than the 14nm lpp allowed and that will likely remedy some of the latency penalty of going across CCX's.

It was set in stone in AMD's roadmaps that they would eventually go to a 48c/96t EPYC chip in the future. That would be a 12 core AM4 chip (x4). I beleive that things are going so well, that AMD might be able to jump the 12 core, and go straight to the 16 core variant. This could very well be an 8 core CCX, but in that case, I would think they would HAVE to have two memory controllers per CCX. I can't see 8c/16t being fed by a single channel memory controller (unless there is some HBM on chip as a L4 cache of sorts). Then again, if the single CCX only has 6c/12t max, it could just get by with a fast DDR4 memory controller. I would guess maybe DDR4-3866 or 4266 as an officially accepted speed (not as an OC speed) would do it. Intel is going 6-8 channel memory in the high end single socket space, and AMD could well follow that, and add more cores, for EPYC. What this would give to AMD, is a single CCX, with 8c/16t, that they can sell all the way down to a 4c/4t. If its dual channel memory capable, they can activate both memory channels when its a single CCX, and maybe only activate one per CCX when its a dual CCX/16c/32t AM4 chip. Or they could use DDR5 (highly unlikely) that would give better bandwith than DDR4, and keep just a single memory channel per CCX (very unlikely). So, my bet is 7nm, up to 16c/32t with two CCX's (maybe only up to 12c/24t on AM4, and keep all the fully enabled die for the Threadrippers/EPYC chips), dual channel memory controller, (8-16 channel on TR/EPYC). You will also get single CCX designs, up to probably 6c/12t, with dual channel memory controller, again, fully enabled CCX's reserved for the TR/EPYC chips. an 8c/16t chip would be dual CCX, half of each active. I'm not sure they would up the L3 to 32Mb, I don't see the need for that, they could quite happily keep 16Mb of L3. The extra cache would really be for the Pro users, and they could buy the TR/EPYC chips, with all the extra memory controllers and bandwidth. Looking forward to the future 🙂

urbancamper:

Also waiting for Zen 2. Found this board at the Egg. https://www.gigabyte.com/us/Motherboard/B450-AORUS-PRO-WIFI-rev-10#kf Oh ya this is 8 phase. Also an AsRock mini that looks like 6 phase

The B350 and B450 are basicly the same board with a doubled 4 phase design. 4+3 with each phase having one 4C10N high side, and two 4C06N low side mosfets. Their x470 has an additional two 4C10N high side mosfets. The Gaming 3 already has heat issues on the VRM's with the 1st gen Ryzen 7 processors. This is board should run fine with anything lower then a 2600X without overclocking.

I would rather just get a cheap X470 board with 8+3 and digi+ VRMs.

Reddoguk:

I would rather just get a cheap X470 board with 8+3 and digi+ VRMs.

But what to do if you have a MicroATX case ????? ITX and ATX have X370/470 support, but the mATX users are left in the lurch...B450 only....

AMDfan:

I heared a rumor that Ryzen2 7Nm will bring 12 to 16 core to the AM4 platform, and gets a 10 to 15% IPC gain over Ryzen 2000 series on 12Nm.

I heard the same. 12c was the plan all along for 7nm, but I think that 16c might be possible. I hope they up the PCIe lane count too next shrink. Not sure what the AM4 socket is capable of. They could always bring out a new socket, i mean the leap from AM4 to TR is Huge (Pincount, everything). edit : Looking at the pinouts between intel and AM4 (1331-1151=180pins) and even taking into account the Display outputs and Sata lanes, you could still get another 16 PCIe lanes in there. So going from 24 lanes in the CPu to 40+ lanes (or 32 to 48, (or even 64 tho the pinout won't allow on AM4), if you go by the server chips that have 128PCIe lanes atm (4xdualCCX's)). Would be sweet 🙂

[youtube=3IjWCOXSuKU] Just wait a few weeks for reviews to land and to have people take a look at VRM's.

GlennB:

[youtube=3IjWCOXSuKU] Just wait a few weeks for reviews to land and to have people take a look at VRM's.

Makes you think, seeing the amount of Intel Boards, vs the number of AMD boards, made by the major manufacturers, if there isn't some sort of "pressure" to make sh!tty AMD boards somehow ? Its not beneath Intel, they've done it before. to slow down the AMD wave or something...

Evildead666:

Makes you think, seeing the amount of Intel Boards, vs the number of AMD boards, made by the major manufacturers, if there isn't some sort of "pressure" to make sh!tty AMD boards somehow ? Its not beneath Intel, they've done it before. to slow down the AMD wave or something...

Competition is fierce in the lower end, saving 1-2 euro's of production costs on a board costing 75 euro (Gigabyte B450 DS3H for example) is huge. On the higher end board's there is enough profit to earn and competition revolves about the little extra's (rgb, extra lan port, more sata etc). They also kind of expect people with a high end processor to buy a high end board. The past has shown this was not always the case ( FX 8300 series combined with poorly designed boards). There are also enough Intel boards where VRM's and VRM cooling is poorly designed and most probably will fail to run a 8700K overclocked.

Evildead666:

I heard the same. 12c was the plan all along for 7nm, but I think that 16c might be possible. I hope they up the PCIe lane count too next shrink. Not sure what the AM4 socket is capable of. They could always bring out a new socket, i mean the leap from AM4 to TR is Huge (Pincount, everything). edit : Looking at the pinouts between intel and AM4 (1331-1151=180pins) and even taking into account the Display outputs and Sata lanes, you could still get another 16 PCIe lanes in there. So going from 24 lanes in the CPu to 40+ lanes (or 32 to 48, (or even 64 tho the pinout won't allow on AM4), if you go by the server chips that have 128PCIe lanes atm (4xdualCCX's)). Would be sweet 🙂

Well from the sound of things with Epic going straight to Zen 2 with apparently 64 cores and 128 threads it sounds like the Zen 2 is going to have twice as many cores per CCX module thanks to the die shrink i personally would like to see higher clock speeds, Ryzen's IPC is only slightly less than Intels around 5% but Intel does have the higher clock speed advantage and would like Zen2 to hit the 4.5GHz mark at least. I was kinda hoping that the Zen+ would have hit that but not quite with it topping around 4.3 and in rare cases 4.4Ghz. With Zen 2 apparently having a 15% IPC increase most likely this will be down to further reduce latency and overhead between CCX's and maybe in the new platform they will got from the interconnect of PCIe 3 4x to PCIe 4 4x doubling it's bandwidth to devices then reduced latency for L1 and L2 cache. Infact AMD has alot of improvements for L1 and L2 cache latency compared to Intel but i guess the very fast L1 and L2 cache will have a large impact on the cost also, but increasing it should yield some better performance gains. There is still alot of tweaking that can be done with Ryzen to get IPC up and the architecture seems to be very scalable.