That graph is strange... how does moving from 14nm to 10nn more than double the transistor density(40mio/mm² @ 14nm -> 100mio/mm² @ 10nm = -28% size, 2.5x density)? Especially if the previous larger shrinks only allowed for a smaller improvement (18mio/mm² @ 22nm -> 40mio/mm² @ 14nm = -36% size, 2.22x density)

Öhr:

That graph is strange... how does moving from 14nm to 10nn more than double the transistor density(40mio/mm² @ 14nm -> 100mio/mm² @ 10nm = -28% size, 2.5x density)? Especially if the previous larger shrinks only allowed for a smaller improvement (18mio/mm² @ 22nm -> 40mio/mm² @ 14nm = -36% size, 2.22x density)

Because transistors are not cubes. They have odd shapes and are susceptible to interference or electron tunneling if placed too close to one another. The drop is measured size vs. die area depends on which axis were shrunk and by how much. Their "size" is also measured differently by different companies. Intel's 14nm process is smaller than global foundries 14nm (which would be about 18nm if they were measured the way Intel measures). To get a better picture of the possible density we need to know the exact size along all three axis as well as the required void space between components to know how much area they use and how closely they can be packed. At the moment those details aren't available yet for the 10nm process, just the density.

Also recall when Intel moved to using FinFets back when they were at 22nm ie "transistors in the 3d dimension" they called it. People gloss over this all the time but now chips are 3d the nanometers taken from the smallest feature the lithography can make really doesn't mean much anymore. It meant a lot more back when chips were "2d" since it directly contributed to the gate length which had a fairly predictable shrink but it was mostly marketing then too. So the little fins that stick up like a microscopic sharks fin contribute a lot to density as well. Instead of just measuring width you now have to account for the length and the pitch or what angle the pieces lean over on the 3d pieces. I tried to keep this rather high level on purpose. The short of it is lithography feature size doesn't translate to densities anymore since chips are now in 3d.

Great explanation guys, thanks for helping us better understand what is going on!