Commit: drm/amdgpu: add gmc ip block for sienna_cichlid
Hilbert, please don't use WCCFTech as a source.
Anyway, Cichlids are freshwater fishes living in a lakes... here we have a clear allusion to Intel's xxxx Lake
Navi23 perhaps or how the naming goes, think there's 21 to 23 possibly others maybe also plans on integrated or mobile chips replacing Vega.
Names and such have been dug up for a while now, no idea what the launch lineup will be of course but it looks like AMD's covering high to low range along with further work with Apple and the workstation WX type cards if I remember their names correctly.
Rest of it seems to get a bit confusing or mixing in more rumors anything from GDDR6 to HBM and 128 up to 384-bit bus with some even going for 512-bit although that looks a bit unlikely personally but who knows.
If it's going to be expensive AMD could try to go at it like the 290 was supposed to be but if they can barely edge out over the existing 2000 lineup from NVIDIA in terms of performance that's going to be a problem when Ampere is on the market or if Ampere is on the market first.
EDIT: Nice to see more driver code and commits through the Linux code submissions though, means it's getting there for a possible late Autumn reveal and whenever it's supposed to launch.
if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1)
This is from gmc10 code in mainline kernel
/**
* gmc_v10_0_mc_init - initialize the memory controller driver params
*
* @adev: amdgpu_device pointer
*
* Look up the amount of vram, vram width, and decide how to place
* vram and gart within the GPU's physical address space.
* Returns 0 for success.
*/
static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
{
int chansize, numchan;
if (!amdgpu_emu_mode)
adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
else {
/* hard code vram_width for emulation */
chansize = 128;
numchan = 1;
adev->gmc.vram_width = numchan * chansize;
}
+ if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) { + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ + } else { + r = amdgpu_atomfirmware_get_vram_info(adev, + &vram_width, &vram_type, &vram_vendor); + adev->gmc.vram_width = vram_width; + + adev->gmc.vram_type = vram_type; + adev->gmc.vram_vendor = vram_vendor; + }Commit: drm/amdgpu: add gmc ip block for sienna_cichlid Hilbert, please don't use WCCFTech as a source. Anyway, Cichlids are freshwater fishes living in a lakes... here we have a clear allusion to Intel's xxxx Lake/** * gmc_v10_0_mc_init - initialize the memory controller driver params * * @adev: amdgpu_device pointer * * Look up the amount of vram, vram width, and decide how to place * vram and gart within the GPU's physical address space. * Returns 0 for success. */ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) { int chansize, numchan; if (!amdgpu_emu_mode) adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); else { /* hard code vram_width for emulation */ chansize = 128; numchan = 1; adev->gmc.vram_width = numchan * chansize; }So you are right, that applies to emulation mode