AMD Sienna Cichlid spotted in Linux Kernel patches, Big Navi?

by Hilbert Hagedoorn on: 06/02/2020 08:35 AM | source: phoronix.com | 5 comment(s)

New Linux kernel patches show mention of AMD "Sienna Cichlid" GPU, which could be the "Big Navi" GPU. And I mean, hey it's got to be released at some point in time, Q3 seems pretty valid.

The codename is pretty unusual though. The patches indicate Sienna Cichlid is a Navi-based GPU with new VCN 3.0 capabilities for video encoding and DCN3 on the display front and a variety of other alterations compared to the existing Navi support, as Phoronix spotted:

It's quite possible Sienna Cichlid is the "big Navi" / RDNA2 GPU. AMD developers have talked before of using alternative codenames when volleying patches early for their open-source Linux driver stack as to not reveal the product/marketing codenames, which could be the case here. This is the first time we are hearing of Sienna Cichlid or seeing any references on the web of it related to AMD. Given the timing of these patches, the AMD Sienna Cichlid won't be mainlined until the Linux 5.9 merge window opening in August and then releasing in stable around October. That timeframe at least does point to Sienna Cichlid likely being the "RDNA 2" graphics card launch coming later in the calendar year.

Update: this is definitely not Big Navi as the memory bus is read out as 128-bit wide as forum member krtec noticed.... :)

+ if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) {
+ adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
+ } else {
+ r = amdgpu_atomfirmware_get_vram_info(adev,
+ &vram_width, &vram_type, &vram_vendor);
+ adev->gmc.vram_width = vram_width;
+
+ adev->gmc.vram_type = vram_type;
+ adev->gmc.vram_vendor = vram_vendor;
+ }

Krteq
Senior Member

Posts: 655
Joined: 2009-09-03

#5794893 Posted on: 06/02/2020 08:31 AM

"Big Navi"?

Checked a commit and it clearly states 128-bit bus and GDDR6.

+    if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) {
+        adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
         adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
+    } else {
+        r = amdgpu_atomfirmware_get_vram_info(adev,
+                &vram_width, &vram_type, &vram_vendor);
+        adev->gmc.vram_width = vram_width;
+
+        adev->gmc.vram_type = vram_type;
+        adev->gmc.vram_vendor = vram_vendor;
+    }

Commit: drm/amdgpu: add gmc ip block for sienna_cichlid

Hilbert, please don't use WCCFTech as a source.

Anyway, Cichlids are freshwater fishes living in a lakes... here we have a clear allusion to Intel's xxxx Lake

JonasBeckman
Senior Member

Posts: 16851
Joined: 2009-02-25

#5794906 Posted on: 06/02/2020 09:52 AM

Navi23 perhaps or how the naming goes, think there's 21 to 23 possibly others maybe also plans on integrated or mobile chips replacing Vega.
Names and such have been dug up for a while now, no idea what the launch lineup will be of course but it looks like AMD's covering high to low range along with further work with Apple and the workstation WX type cards if I remember their names correctly.

Rest of it seems to get a bit confusing or mixing in more rumors anything from GDDR6 to HBM and 128 up to 384-bit bus with some even going for 512-bit although that looks a bit unlikely personally but who knows.
If it's going to be expensive AMD could try to go at it like the 290 was supposed to be but if they can barely edge out over the existing 2000 lineup from NVIDIA in terms of performance that's going to be a problem when Ampere is on the market or if Ampere is on the market first.

EDIT: Nice to see more driver code and commits through the Linux code submissions though, means it's getting there for a possible late Autumn reveal and whenever it's supposed to launch.

Martin2603PL
Member

Posts: 25
Joined: 2014-08-24

#5794921 Posted on: 06/02/2020 10:30 AM

AMD "Ariel" is more interesting piece in terms of XSX vs PS5 (Ariel is older GPU compared to XBX)

Komachi
Member

Posts: 29
Joined: 2015-05-29

#5795112 Posted on: 06/03/2020 02:12 AM

New Linux kernel patches show mention of AMD "Sienna Cichlid" GPU, which could be the "Big Navi" GPU. And I mean, hey it's got to be released at some point in time, Q3 seems p...

AMD Sienna Cichlid spotted in Linux Kernel patches, Big Navi?

"adev->gmc.vram_width = 1 * 128; /* numchan * chansize */" was not added in this patch.
This code has been around for a while.
If I'm not mistaken, the code of "adev->gmc.vram_width = 1 * 128; /* numchan * chansize */" in this emulate mode is what is used by all GFX10 ASICs (Navi 1X/Navi 2X).
So, all we only know from these patches is that "AMD Sienna Cichlid" will use GDDR6.
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=amd-staging-drm-next-sienna-cichlid&id=bb1de01b29185f9cef8c6c347eed7c0fd9e64188

Krteq
Senior Member

Posts: 655
Joined: 2009-09-03

#5795179 Posted on: 06/03/2020 10:37 AM

Jeezzz, my bad.. I ignored this part

ops:

if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1)

This is from gmc10 code in mainline kernel

/**
 * gmc_v10_0_mc_init - initialize the memory controller driver params
 *
 * @adev: amdgpu_device pointer
 *
 * Look up the amount of vram, vram width, and decide how to place
 * vram and gart within the GPU's physical address space.
 * Returns 0 for success.
 */
static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
{
    int chansize, numchan;

    if (!amdgpu_emu_mode)
        adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
    else {
        /* hard code vram_width for emulation */
        chansize = 128;
        numchan = 1;
        adev->gmc.vram_width = numchan * chansize;
    }

So you are right, that applies to emulation mode

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