AMD Ryzen 3000: New Block diagram about PCIe 4.0 on Matisse and X570 chipset

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I thought the 40 lanes reported the other week seemed excessive. I don't like the look of the m.2 configuration unless the 2xPCIe4 can be effectively split into 4xPCIe3, Otherwise current cards would probably end up at 2xPCIe3 speed?
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Stairmand:

I thought the 40 lanes reported the other week seemed excessive. I don't like the look of the m.2 configuration unless the 2xPCIe4 can be effectively split into 4xPCIe3, Otherwise current cards would probably end up at 2xPCIe3 speed?
Such a controller that can split x2 4.0 into x4 3.0 would probably be very expensive, and not likely to be present. But the 4 M.2 PCIe lanes from the CPU can be used as one for one x4 device as well, it doesn't have to be split into 2x x2.
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such a controller can be had for a few dollars.
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nevcairiel:

Such a controller that can split x2 4.0 into x4 3.0 would probably be very expensive, and not likely to be present. But the 4 M.2 PCIe lanes from the CPU can be used as one for one x4 device as well, it doesn't have to be split into 2x x2.
Just having 1 4xPCIe M.2 slot would be a disappointing mistake. Prices have dropped to the point where having a 250GB Boot and 2TB second nvme drive are realistic options. Certainly what i would buy in my next setup.
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Stairmand:

Just having 1 4xPCIe M.2 slot would be a disappointing mistake. Prices have dropped to the point where having a 250GB Boot and 2TB second nvme drive are realistic options. Certainly what i would buy in my next setup.
Just like any previous boards and chipsets, the second would be through the chipset.
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Stairmand:

I don't like the look of the m.2 configuration unless the 2xPCIe4 can be effectively split into 4xPCIe3
nevcairiel:

the 4 M.2 PCIe lanes from the CPU can be used as one for one x4 device as well, it doesn't have to be split into 2x x2.
Sure, it's up to motherboard manufacturers to decide how they would trace the on-die PCIe/SATA lanes. I'd think most of them would map these PCIe 4.0 x4 lanes to a single M-key M.2 slot.
nevcairiel:

Such a controller that can split x2 4.0 into x4 3.0 would probably be very expensive, and not likely to be present.
No, it's not expensive. Signal downconversion is what the X470 actually did - it only provided PCIe 2.0 lanes for its M.2/PCIe/controller connections, and most boards had quite slow PCIe 2.0 x2 for the secondary M.2 slot, though a few offered PCIe 2.0 x4. That's 1/4 or 1/2 of the available PCIe 3.0 x4 bandwidth from the X470 PCH to the CPU.
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DmitryKo:

No, it's not expensive. Signal downconversion is what the X470 actually did - it only provided PCIe 2.0 lanes for its M.2/PCIe/controller connections, and most boards had quite slow PCIe 2.0 x2 for the secondary M.2 slot, though a few offered PCIe 2.0 x4. That's 1/4 or 1/2 of the available PCIe 3.0 x4 bandwidth from the X470 PCH to the CPU.
This was integrated into the chipset, which has a PCIe hub controller anway, and not offered for the CPU lanes (which he was requesting), which are often connected directly without further controller in between. Additionally, PCIe 3.0 and 2.0 are old and known technology, 4.0 is new, so any such hardware can be expected to be more expensive. Personally, for future proofing, I would want my CPU 4x lanes connected directly to a PCIe 4.0 x4 M.2 slot, so that I can run a fast PCIe 4.0 NVMe drive in there in the future.
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Aren't current PCIe lanes plenty for most nvme drivers? I mean, 2x PCIe 4 lanes should equal a 4x PCIe 3, and isn't that enough for 99% of the cases? Future proof is definetly a thing, but let's not put the cart ahead of the horses, okay?
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Yes 2 x PCIe 4 is the same speed as 4xPCIe 3, however all current SSDs are PCIe 3 only, if they only have access to 2 lanes they will be at PCIe 3 speed limiting performance. Many current drives already need all 4 lanes. Unless of course board manufactures have only one nvme compatible socket and use all 4 lanes. Or come up with a solution using pcie switches etc. I guess we will se next week. I suspect it won't be long before we see PCIe4 SSDs go past the 4000MB/s speed.
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PCI-E3 parts will benefit from gen 4 controllers in ways just gen 2 parts benefitted from gen 3 controllers. Thats not the point of why they have introduced gen 4 though. being able to reduce the lane count for nvme's and not losing performance is a reason why.
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In the diagram there are many options for different builds. MSI is showing a Pro Carbon motherboard where I can read "LIGHTNING Gen4 m.2" written in it's shield, so I assume it will be 4x PCIe 4 in this model. Anyway, we'll know the next week 😉
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Stairmand:

I thought the 40 lanes reported the other week seemed excessive. I don't like the look of the m.2 configuration unless the 2xPCIe4 can be effectively split into 4xPCIe3, Otherwise current cards would probably end up at 2xPCIe3 speed?
The 40 lanes was just a misreading of the leak and a lack of comprehension about how chipsets work. It was never going to be 40 lanes, that's ridiculous. The current Ryzen CPUs with, for example, X470, are 24 PCie 3.0 lanes: 16x for GPU, 4x dedicated to M.2, 4x upstream for the chipset. The chipset itself is 8x PCIe 2.0 downstream. The X570 is double this - 24x PCIe 4.0 lanes - with 16x, 4x, 4x, with an unknown amount/speed for downstream, although anticipated is 16x PCIe 4.0. For comparison, Z370/390 is only 20 PCie 3.0 lanes (16x GPU, 4x DMI 3.0), the 24x downstream over chipset (16x engaged at once) are just multiplexed. To go back to the original leak: it was not saying lanes for each category, in fact it clearly said x4 Gen4 for uplink (chipset upstream) with 16 for GPU (PCIe: 8 + 4 + 4 means up to 3 GPUs with bifurcation), it was misread as I said. And the new diagram simply shows 4x PCIe 4.0 coming from CPU for SATA/NVMe in addition to SATA/NVMe over the chipset (similar to the 4x PCIe 3.0 on X470 for a primary M.2). So pretty straightforward and as expected, actually. To answer the M.2 question: no, you can switch 2x PCIe 4.0 into 4x PCIe 3.0. Many existing boards switch 4x PCIe 2.0 into 2x PCIe 3.0 for M.2, for example. I suspect also that in some cases 4x PCIe 4.0 will be supported which will regress to 4x PCIe 3.0 if the drive is 3.0.
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Stairmand:

I suspect it won't be long before we see PCIe4 SSDs go past the 4000MB/s speed.
The Phison E16 drives will hit 5000/4400 MB/s R/W. One I know of already is the Gigabyte Aorus Gen4 NVMe.
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oh now makes sense the need for the fan on that south bridge. It will probably kick in if you are using a config on which you are maxing out the controller with Gen3 configs like using all the PCIe lanes.
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nevcairiel:

Just like any previous boards and chipsets, the second would be through the chipset.
Except unlike previous boards that second slot on the chipset won't be bottlenecked by the link between the chipset and CPU. An x4 link can run a pcie 3.x x4 SSD at full speed while using the USB and networking without saturating the bus, unlike current Intel and AMD desktop boards. It also will not be long before someone builds a bridge board that will run 4 pcie 3.x x4 SSDs at full speed in the second x8 video card slot and ones that will run x2 SSDs in the x1 slots. In the end, though, there are still almost zero use cases when a pcie SSD actually shaves more than a minute or two off an entire day's work vs a SATA one, so the dream of >6k transfers on pcie 4.x is in the end pretty moot for the foreseeable future.
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nevcairiel:

This was integrated into the chipset, which has a PCIe hub controller anway, and not offered for the CPU lanes (which he was requesting) I would want my CPU 4x lanes connected directly to a PCIe 4.0 x4 M.2 slot, so that I can run a fast PCIe 4.0 NVMe drive in there in the future.
Standalone 6-lane 5-port PCIe switches cost $30-50 per chip, though I agree there is no point to use them to downconvert CPU lines and lose full PCIe 4.0 x4 bandwidth.
Astyanax:

PCI-E3 parts will benefit from gen 4 controllers in ways just gen 2 parts benefitted from gen 3 controllers. being able to reduce the lane count for nvme's and not losing performance is a reason why.
There will be no benefit at all, since gen 3 parts will only be able to communicate at gen 3 speeds and reduced line count would compromise the ransfer rate for older devices.
NewMaxx:

Many existing boards switch 4x PCIe 2.0 into 2x PCIe 3.0 for M.2, for example
Are there reviews confirming that these M.2 slots actually work in PCIe 3.0 x2 mode, and this is not an error in the specs? Theoretically they could bypass the PCH and directly connect the secont M.2 slot to the CPU, but the only benefit would be slightly higher peak bandwidth from using 128b/130b encoding. There would be absolutely no benefits for upconverting PCIe 2.0 x4 from the PCH into PCIe 3.0 x2.
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DmitryKo:

There will be no benefit at all, since gen 3 parts will only be able to communicate at gen 3 speeds and reduced line count would compromise the ransfer rate for older devices.
Afraid you're applying a very limited understanding of the hardware here.
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just to remember the bus between CPU and x570 is x4 4.0 (which is a lot for most of the common users that have 1 or 2 storage devices), everything that's not directly connected with the CPU could be limited if in concurrency with other devices... so all those bandwidth from the chipset you are demanding is simply fancy..
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Astyanax:

you're applying a very limited understanding of the hardware
Am I?
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DmitryKo:

Are there reviews confirming that these M.2 slots actually work in PCIe 3.0 x2 mode, and this is not an error in the specs?
Definitely exist. Example would be the Prime X470-PRO's M.2_2 socket. The reason they do this is to assist PCIe 3.0 x2 drives which are limited to 2 lanes even if the M.2 socket is 4x PCIe 2.0. There's a lot of these: WD SN500, any of the E8/E8T drives, SX6000NP, etc. In that board's case the socket shares a PCIe clock with one PCIe x1 slot and bandwidth with two PCIe slots (these slots share bandwidth with the x4 electrical x16 physical PCIe slot from PCH). I'd say this was an error but I've seen multiple boards as such, like the TUF X470 Plus Gaming, although some of their boards allow x4 PCIe 3.0 by pulling lanes from GPU.