AMD Ryzen 3000: New Block diagram about PCIe 4.0 on Matisse and X570 chipset
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Stairmand
I thought the 40 lanes reported the other week seemed excessive. I don't like the look of the m.2 configuration unless the 2xPCIe4 can be effectively split into 4xPCIe3, Otherwise current cards would probably end up at 2xPCIe3 speed?
nevcairiel
Astyanax
such a controller can be had for a few dollars.
Stairmand
nevcairiel
DmitryKo
nevcairiel
Ricardo
Aren't current PCIe lanes plenty for most nvme drivers? I mean, 2x PCIe 4 lanes should equal a 4x PCIe 3, and isn't that enough for 99% of the cases?
Future proof is definetly a thing, but let's not put the cart ahead of the horses, okay?
Stairmand
Yes 2 x PCIe 4 is the same speed as 4xPCIe 3, however all current SSDs are PCIe 3 only, if they only have access to 2 lanes they will be at PCIe 3 speed limiting performance. Many current drives already need all 4 lanes.
Unless of course board manufactures have only one nvme compatible socket and use all 4 lanes. Or come up with a solution using pcie switches etc.
I guess we will se next week. I suspect it won't be long before we see PCIe4 SSDs go past the 4000MB/s speed.
Astyanax
PCI-E3 parts will benefit from gen 4 controllers in ways just gen 2 parts benefitted from gen 3 controllers.
Thats not the point of why they have introduced gen 4 though.
being able to reduce the lane count for nvme's and not losing performance is a reason why.
Luc
In the diagram there are many options for different builds.
MSI is showing a Pro Carbon motherboard where I can read "LIGHTNING Gen4 m.2" written in it's shield, so I assume it will be 4x PCIe 4 in this model.
Anyway, we'll know the next week 😉
NewMaxx
NewMaxx
neikosr0x
oh now makes sense the need for the fan on that south bridge. It will probably kick in if you are using a config on which you are maxing out the controller with Gen3 configs like using all the PCIe lanes.
illrigger
DmitryKo
Astyanax
Alessio1989
just to remember the bus between CPU and x570 is x4 4.0 (which is a lot for most of the common users that have 1 or 2 storage devices), everything that's not directly connected with the CPU could be limited if in concurrency with other devices... so all those bandwidth from the chipset you are demanding is simply fancy..
DmitryKo
NewMaxx