The PCI-SIG, the consortium responsible for the development of the PCI Express (PCIe) standards, has recently made public the initial draft, version 0.5, of the forthcoming PCIe 7.0 specification. This marks the first official draft of the specification distributed to members of the PCI-SIG. This new iteration, set to succeed the PCIe 6.0 standard introduced in early 2022, proposes to double the data transfer rate once more, maintaining the use of PAM4 (Pulse Amplitude Modulation with 4 levels) signaling. The projected data transfer rate for PCIe 7.0 is 128 GT/s (GigaTransfers per second) per lane, with a potential bandwidth of 512 GB/s (Gigabytes per second) in a x16 configuration, offering significant improvements over its predecessor.

The PCIe 7.0 specification is being developed with an emphasis on enhancing channel performance, reach, and energy efficiency. Its goal is to provide more robust interconnect solutions tailored for demanding data-centric applications, including 800G Ethernet, artificial intelligence and machine learning workloads, ultra-scale data centers, high-performance computing, quantum computing, and cloud services. According to the PCI-SIG, the finalized version 1.0 of the PCIe 7.0 standard is anticipated to be ready by 2025, aligning with the current pace of development.

In the industry, Alphawave Semi has already introduced products related to PCIe 7.0 signal generation and measurement technologies earlier this year, indicating early moves towards adoption. For the general consumer market, the transition to PCIe 7.0 remains on the horizon. As of now, consumer hardware predominantly supports up to PCIe 5.0, with PCIe 6.0 compatible products yet to emerge in the mainstream market.