At the InnovatiON 2023 Day 1 Q&A, Intel CEO Pat Gelsinger discussed the company's ongoing work in 3D-stacked cache technology for their processors. The technique involves expanding the on-die last-level cache (L3 cache) by stacking an additional SRAM die atop the current cache, integrating it with the cache's high-bandwidth data fabric.

Interestingly, the stacked cache operates at the same velocity as the on-die cache, offering a continuous addressable cache memory block. Although this technology is not slated for the Meteor Lake, Intel plans its implementation in various future processors. AMD has already integrated 3D-stacked cache technology into its processors, yielding significant results. In client processors, such as the Ryzen X3D series, the augmented cache notably enhances gaming performance by enabling the CPU cores to swiftly access more rendering data. For server processors, models like EPYC "Milan-X" and "Genoa-X" have seen marked performance boosts in memory-heavy computational tasks, attributed to the increased cache.

Example of AMD's iteration of 3D cache

Gelsinger's clarification highlighted the hardware-level differentiation in Intel's 3D-stacked cache technology compared to AMD's. AMD's rendition stems from a partnership with TSMC, adopting the TSMC-forged SoIC (System-on-Integrated-Chip) packaging technology. This facilitates dense die-to-die wiring between the CCD (Core Chiplet Die) and the cache chiplet. On the other hand, Intel, utilizing its in-house fabs for processor manufacturing, has incorporated its proprietary technology.

Source: Tom's Hardware