3nm?! thats truly incredible to hear, & heartening that theyre putting in such an investment. that being said, ill be borderline disappointed if it ends up being some 5nm-with-wings uarch

__hollywood|meo:

3nm?! thats truly incredible to hear, & heartening that theyre putting in such an investment. that being said, ill be borderline disappointed if it ends up being some 5nm-with-wings uarch

That is not really real 3nm in sense that it can be compered to Intel's 3nm,more like marketing gimmick 3nm

What does the size 3/5/7nm mean these days? As far as I understand it that naming convention hasn't applied since 32nm because of the introduction of finFET transistors

Yogi:

What does the size 3/5/7nm mean these days? As far as I understand it that naming convention hasn't applied since 32nm because of the introduction of finFET transistors

Basically only Intel sticks to the original measurements, thats why Intel is still calling theirs 14nm while most of everyone else is sporting "10nm" - which in reality isn't smaller/better then Intels 14nm - and Intels 10nm will probably be about similar to everyones elses 7nm. Unfortunately without a real deep insight into their processes, its otherwise hard to really compare them. The only thing one can know is that TSMC "3nm" is smaller (better?) then TSMC "7nm", but thats about it. On top of that new processes may not be quite as efficient as older processes, resulting in them only being used for low-power devices at first.

3nm! We're really at the limit of what silicon can do here aren't we, I mean it'd be impossible to ever have silicon chips designed at less than 1nm right? Think I vaguely read that somewhere. So, if that's the case, not many years left of shrinkage available to the silicon based technology. EDIT: did some reading around the subject just now. Looks like 3nm might be the limit for silicon chip shrinkage - at which point other technologies will need to come into play, like maybe stacking layers of silicon chips on top of each other, or other technologies based on other materials than silicon.

nevcairiel:

Basically only Intel sticks to the original measurements, thats why Intel is still calling theirs 14nm while most of everyone else is sporting "10nm" - which in reality isn't smaller/better then Intels 14nm - and Intels 10nm will probably be about similar to everyones elses 7nm. Unfortunately without a real deep insight into their processes, its otherwise hard to really compare them. The only thing one can know is that TSMC "3nm" is smaller (better?) then TSMC "7nm", but thats about it. On top of that new processes may not be quite as efficient as older processes, resulting in them only being used for low-power devices at first.

Do you have sources on this? I'm not calling you a liar, I'm legitimately interested in reading more about this. I kind of thought 3nm was too good to be true, though even if it's more like 6nm, that's still seriously impressive.

Yogi:

What does the size 3/5/7nm mean these days? As far as I understand it that naming convention hasn't applied since 32nm because of the introduction of finFET transistors

to quote Laurie Anderson - "Big Science". Extreme Ultra Violet lithography.

happily surprised, not shocked given the Taiwanese gov't.'s infrastructure plans released this fall. what a legacy for Morris Chang. taking Apple's A8 and A10 processor's to the bank and reinvesting (a bit more than half) the profit in the last three process node's and ditching Samsung's lpp (low performance processor LOLZ) tech and changing development paths have led to this momentous announcement. if it's not exactly true, it is entirely foreseeable and will be announced at the "right" time.

Yogi:

What does the size 3/5/7nm mean these days? As far as I understand it that naming convention hasn't applied since 32nm because of the introduction of finFET transistors

It just denotes the toolset size for the fab process.

nevcairiel:

Basically only Intel sticks to the original measurements, thats why Intel is still calling theirs 14nm while most of everyone else is sporting "10nm" - which in reality isn't smaller/better then Intels 14nm - and Intels 10nm will probably be about similar to everyones elses 7nm. Unfortunately without a real deep insight into their processes, its otherwise hard to really compare them. The only thing one can know is that TSMC "3nm" is smaller (better?) then TSMC "7nm", but thats about it. On top of that new processes may not be quite as efficient as older processes, resulting in them only being used for low-power devices at first.

Actually not even Intel is sticking to "original measurement"(OM) . Even Intel admits that fact, but to give them credit they are "closest" to OM ,problem is that there is not even single feature on 14nm that is 14nm ,some are bigger but there is some that are even smaller then 14nm.That "14nm" is just marketing term denoting OM, meaning today's "14nm" with it's FinFet ,narrow but tall fins,high-k materials ... would equate to OM 14nm

Yogi:

What does the size 3/5/7nm mean these days? As far as I understand it that naming convention hasn't applied since 32nm because of the introduction of finFET transistors

okay, heres the thing. 16/14nm finfet is basically 20nm + transistors. the concept behind the design is inspired, but 16/14nm finfet nodes are essentially ~just~ highly optimized 20nm in actual physical scale/density. the backend, the ~root~ of the chip, was the same in 1st gen "shrinks" from 20nm via GloFo, samsung, & TSMC. intel made efforts to do a legit die shrink & was more successful initially...however, 2nd gen finfet from samsung especially had significant optimization/power reductions as the process was now legitimately increasing in density. 2nd gen from intel was yawn inducing by comparison, with little to no power drop - indicating that its about as mature as its going to get. the takeaway here is that each """""shrink""""" from 20nm has been a literal half step coupled with aggressive marketing. 7/10nm is a stones throw from mature 14/16nm node in sad actuality. if i had to hazard a guess, TSMC researching/marketing 3nm process might equate to them pursuing an honest 7nm node in physical lithographical structure. whether they can do it remains to be seen, but with 20bn, they will certainly come up with some advancement in uarch

__hollywood|meo:

okay, heres the thing. 16/14nm finfet is basically 20nm + transistors. the concept behind the design is inspired, but 16/14nm finfet nodes are essentially ~just~ highly optimized 20nm in actual physical scale/density. the backend, the ~root~ of the chip, was the same in 1st gen "shrinks" from 20nm via GloFo, samsung, & TSMC. intel made efforts to do a legit die shrink & was more successful initially...however, 2nd gen finfet from samsung especially had significant optimization/power reductions as the process was now legitimately increasing in density. 2nd gen from intel was yawn inducing by comparison, with little to no power drop - indicating that its about as mature as its going to get. the takeaway here is that each """""shrink""""" from 20nm has been a literal half step coupled with aggressive marketing. 7/10nm is a stones throw from mature 14/16nm node in sad actuality. if i had to hazard a guess, TSMC researching/marketing 3nm process might equate to them pursuing an honest 7nm node in physical lithographical structure. whether they can do it remains to be seen, but with 20bn, they will certainly come up with some advancement in uarch

all marketing aside, yes. it is still impressive in the extreme. this (imo) completely validates Morris Chang's very controversial decision to ditch the Samsung accord. and the gov't of Taiwan is responding in infrastructure commensurate to the well being of it's golden geese (TSMC being the biggest). which will amount to the shortest time to market in the Pacific Rim.

Moore's Law.

$20 billion? That's what... 200 Bitcoins?