Yep. Even when they shave the die size down for commercial products, it's still going to be huge. For example, if they shrink V100 down by the ratio that the 1080 was to P100, it's still larger than GP102 in the 1080Ti.

I kindly believe prices will go up for a maximum of 200$ for titan, 150$ for TI, 100$ for x80, 75$ for x70 and 50$ for x60. Meaningless differences I suppose.

Wait what? 1080 was GP104.

Yep. Even when they shave the die size down for commercial products, it's still going to be huge. For example, if they shrink V100 down by the ratio that the 1080 was to P100, it's still larger than GP102 in the 1080Ti.

I kindly believe prices will go up for a maximum of 200$ for titan, 150$ for TI, 100$ for x80, 75$ for x70 and 50$ for x60. Meaningless differences I suppose.

800mm that's crazy. They must have very high confidence in the fab or are willing to ask a kidney from consumers.

How can you say that? You forgot how much nvidia asked for Pascal FE cards when it came out? You will be paying 500$ for the 2070.

It's 15 TFLOPS for Gaming

Just for random thought: 1170(volta) 11 tflops 1180(volta) 13 tflops 1180ti/titan 15 tflops

That's why Polaris is great at just 232mm^2. The smaller the chip the more they can fit in a single wafer and make it more affordable. Having high performance is great but it would be awesome if everyone could afford it! They are already expensive af. Even if they can use 90% of the dies, it will have less dies per wafer. So each die will be more expensive. 800mm^2 is completely nuts. I'm sure the full Volta GPU will cost about $1499. 2080 will cost about $999. 2070 $500? nah... That die size could be bad, if they had any competition. AMD will take 1 or 2 years to make something after Vega.

Question. Does the 800mm^2 include HBM?

https://devblogs.nvidia.com/parallelforall/wp-content/uploads/2017/05/image3.png Apparently the die mm2 includes the HBM2/Interposer. So the actual die is smaller. Also the tensor units are why FP32 is low given the die size itself. The tensor units most likely won't be on the gaming cards - or will be severely cut down. Along with the FP64. Edit: I guess I could have appended this to my previous post. Sorry.

The big news I'm getting out of this is that Volta has had a third process switch and it's now again at 16/12nm. Which means it will most likely come for consumer products earlier than the end of Q1 2018, as initially predicted. The gaming teraflop numbers aren't exactly crazy though, an overclocked 1080Ti will get close to these. That's pretty much a 2GHz 1080Ti. It's not as huge a leap as I imagined it to be, so I'm curious what different things the actual architecture holds. They seem to have gone very wide this time, I wonder if other architectural details are different or this is "just" a wider Pascal. Interesting times ahead. And yes, that chip is massive.

New Streaming Multiprocessor (SM) Architecture Optimized for Deep Learning Volta features a major new redesign of the SM processor architecture that is at the center of the GPU. The new Volta SM is 50% more energy efficient than the previous generation Pascal design, enabling major boosts in FP32 and FP64 performance in the same power envelope. New Tensor Cores designed specifically for deep learning deliver up to 12x higher peak TFLOPs for training. With independent, parallel integer and floating point datapaths, the Volta SM is also much more efficient on workloads with a mix of computation and addressing calculations. Volta’s new independent thread scheduling capability enables finer-grain synchronization and cooperation between parallel threads. Finally, a new combined L1 Data Cache and Shared Memory subsystem significantly improves performance while also simplifying programming. Second-Generation NVLink™ The second generation of NVIDIA’s NVLink high-speed interconnect delivers higher bandwidth, more links, and improved scalability for multi-GPU and multi-GPU/CPU system configurations. GV100 supports up to 6 NVLink links at 25 GB/s for a total of 300 GB/s. NVLink now supports CPU mastering and cache coherence capabilities with IBM Power 9 CPU-based servers. The new NVIDIA DGX-1 with V100 AI supercomputer uses NVLink to deliver greater scalability for ultra-fast deep learning training. HBM2 Memory: Faster, Higher Efficiency Volta’s highly tuned 16GB HBM2 memory subsystem delivers 900 GB/sec peak memory bandwidth. The combination of both a new generation HBM2 memory from Samsung, and a new generation memory controller in Volta, provides 1.5x delivered memory bandwidth versus Pascal GP100 and greater than 95% memory bandwidth efficiency running many workloads. Volta Multi-Process Service Volta Multi-Process Service (MPS) is a new feature of the Volta GV100 architecture providing hardware acceleration of critical components of the CUDA MPS server, enabling improved performance, isolation, and better quality of service (QoS) for multiple compute applications sharing the GPU. Volta MPS also triples the maximum number of MPS clients from 16 on Pascal to 48 on Volta. Enhanced Unified Memory and Address Translation Services GV100 Unified Memory technology in Volta GV100 includes new access counters to allow more accurate migration of memory pages to the processor that accesses the pages most frequently, improving efficiency for accessing memory ranges shared between processors. On IBM Power platforms, new Address Translation Services (ATS) support allows the GPU to access the CPU’s page tables directly. Cooperative Groups and New Cooperative Launch APIs Cooperative Groups is a new programming model introduced in CUDA 9 for organizing groups of communicating threads. Cooperative Groups allows developers to express the granularity at which threads are communicating, helping them to express richer, more efficient parallel decompositions. Basic Cooperative Groups functionality is supported on all NVIDIA GPUs since Kepler. Pascal and Volta include support for new Cooperative Launch APIs that support synchronization amongst CUDA thread blocks. Volta adds support for new synchronization patterns. Maximum Performance and Maximum Efficiency Modes In Maximum Performance mode, the Tesla V100 accelerator will operate unconstrained up to its TDP (Thermal Design Power) level of 300W to accelerate applications that require the fastest computational speed and highest data throughput. Maximum Efficiency Mode allows data center managers to tune power usage of their Tesla V100 accelerators to operate with optimal performance per watt. A not-to-exceed power cap can be set across all GPUs in a rack, reducing power consumption dramatically, while still obtaining excellent rack performance. Volta Optimized Software New versions of deep learning frameworks such as Caffe2, MXNet, CNTK, TensorFlow, and others harness the performance of Volta to deliver dramatically faster training times and higher multi-node training performance. Volta-optimized versions of GPU accelerated libraries such as cuDNN, cuBLAS, and TensorRT leverage the new features of the Volta GV100 architecture to deliver higher performance for both deep learning and High Performance Computing (HPC) applications. The NVIDIA CUDA Toolkit version 9.0 includes new APIs and support for Volta features to provide even easier programmability.

If these clock similar to Pascal however we may see 18.5-19 Tflop performance with this chip. Also as previously established the die size discussed includes the HBM imposters.

If these clock similar to Pascal however we may see 18.5-19 Tflop performance with this chip. Also as previously established the die size discussed includes the HBM imposters. To your edit. The doubled the tensor core count from GP100. As fare as I know they were not a part of GP102. Does AMD include HBM impossers in their die measurement as I would estimate GV100 at 580~610mm^2 without HBM.

These are apparently the key new features of GV100: New Streaming Multiprocessor (SM) Architecture Optimized for Deep Learning Second-Generation NVLink™ HBM2 Memory: Faster, Higher Efficiency Volta Multi-Process Service Enhanced Unified Memory and Address Translation Services Cooperative Groups and New Cooperative Launch APIs Maximum Performance and Maximum Efficiency Modes Volta Optimized Software Out of all of that, almost zero seems to deal with new deeper architectural stuff. They pretty much seem to have a more optimized/refined memory controller and that's it. The Maximum Performance and Maximum Efficiency modes remind me of similar wording from AMD about Hawaii and Fiji. I don't believe that this one will clock that high this time. We'll see.

New Streaming Multiprocessor (SM) Architecture Optimized for Deep Learning Volta features a major new redesign of the SM processor architecture that is at the center of the GPU. The new Volta SM is 50% more energy efficient than the previous generation Pascal design, enabling major boosts in FP32 and FP64 performance in the same power envelope.