GP100 supports HBM 2 as well as GDDR5 ??? Highly Unlikely

HBM would allow for something like this without having to make 2 different chips.

OMG 225 watts. It will be like a toaster oven.

In what universe is a 512 bit memory interface, clocked at 8000MHZ (effective i can only assume), capable of transfering 512GB data per second. 512 * 4000 (actual clock speed) * 2 (Double Data Rate) = 409.6GB/s transfer speed. To reach 512GB/s on a 512 bit interface, you would need 5GHZ clock speeds (10GHZ effective) As for shader cores and single precision. Assuming that the Pascal chip is of equal size, it seems plausible, considering the reduction from 28nm to 16nm = 57.1% the size. Comparing the 900 series to the 700 series, more specifically the ''Titan black'' which is the most powerful GK110 chip. Compared to the Titan X, which is the most powerful GM200 chip. Titan X 7.1% larger chip 12.9% more transistors 6.6% more Shader cores (nvidia dubbed them ''cuda cores'' 25% fewer Texture Mapping Units 100% more Render output units The 900 series is in practice, a combination of 1. larger chip. 2. improved design. 3. reduction in some areas. and 4. increase in other areas. The production technique, the work done at TSMC is still based on the same 28nm technology, though the yield and quality may have contributed slightly. Comparing the 900 series Titan X and the ''Pascal Titan'' Shader cores = 200% Texture units = 200% Texture mapping units / Raster operators = 200% Transistor count = 204.9% I call bull****. While the speccs may come from Nvidia, i have extreme doubts that these numbers are anything but loosely written down approximations meant for the designers and technicians. Why? I haven't the slightest idea, but i'm guessing it's tough to predict the exact specifications months, or even weeks in advance of large scale production. Doubtless, the guys making the chips, TSMC, cannot guarantee yield quality, thus Nvidia has to work with approximations.

GDDR5 would make sense on an NVIDIA product releasing this year. There is no way that GDDR5X production would ramp up fast enough to cover millions of cards in sales. The speed and width of the GDDR5 make sense too. NVIDIA has had a very effective memory controller on Maxwell, if they translate that to a card with actual 400-500GB/sec bandwidth, they will be fine. By the way, "X" is the latin numeral for "10". So the naming scheme does make a lot of sense. These might be fake, but they do make sense.

In what universe is a 512 bit memory interface, clocked at 8000MHZ (effective i can only assume), capable of transfering 512GB data per second. 512 * 4000 (actual clock speed) * 2 (Double Data Rate) = 409.6GB/s transfer speed. To reach 512GB/s on a 512 bit interface, you would need 5GHZ clock speeds (10GHZ effective)

not buying it, i don't see why nvidia will use gddr5 instead of gddr5x. Also if the titan specs are true, then you can expect a 3k$ price.

Is not latin, its roman number.

Who were the Romans, oh wait, the Latins. :infinity: Roman numerals use letters from the Latin alphabet, and they are alternative known as latin numerals. If the Titan specs are true, it means it will be released in 2017.

The romans spoke latin, they were not the latins

if anyone releases a consumer graphics card with a 600mm^2 die size on 16/14nm finfet this year I'll eat my hat. Also, remind me to buy one of those

Actually going from 28nm down to 16nm is a huge decrease in size, even more than the 57% of the size you talked about. It's because you have to think about silicon chips nm in terms of area (they're 2D structures effectively), so nm-squared. This is the calculation showing theoretically how small 16nm is compared to 28nm: (16x16)/(28*28) = 0.33 Therefore 16nm transistors only take up 33% of the space of their 28nm brothers. (Another way of saying it is that 28nm is 3 times the size (100/33) of 16nm). They skipped a node, that's why they're so much smaller, they skipped the 20nm node. Anyway, I'm not sure I believe this table showing the X80, etc, as me & some others were speculating a couple of days ago with names for the next Pascal architecture, and you can see from Post #1516 on the following page (http://forum.notebookreview.com/threads/pascal-what-do-we-know-discussion-latest-news-updates-1000m-series-gpus.763032/page-152) that we came up with that naming scheme. I reckon someone nicked that idea & just fabbed a spreadsheet.

One of the earliest manufacturing providers at the 14nm process node, Samsung has been developing FinFET process technology for several years and is now ready for early adopter production. Samsung's 14nm LPE process is providing almost 150% better performance from a die half the size of the previous node and improving power consumption by around 150% when compared to its 28nm process technology - See more at: http://www.newelectronics.co.uk/electronics-technology/what-makes-finfets-so-compelling/56795/#sthash.FaHNt2k7.dpuf

Also the 16nm is done on Finfet design compared to planar on 28nm, which has added benefits of better performance and lower power draw in direct comparison transistor for transistor.

Well it's looking better & better for Pascal!