Alder Lake DDR5 Performance Benchmarks Leaks As Well
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Horus-Anhur
Big numbers for memory bandwidth. But also for latency.
On a CPU, usually, latency is much more important than bandwidth.
Mda400
Wonder what it would be like with 1T command rate.
David Lake
Very unstable 😛
Horus-Anhur
Probably it could reduce latency by a few ns. But not much. Maybe 2-4ns.
Just guessing since command rate doesn't have that big impact in memory latency.
But there's one thing to consider.
Those timings are very lose.
Cl40 @ 6400 means an absolute latency of 12.5 ns.
For comparison, CL16 @ 3800 gives an absolute latency of 8.4 ns
For that kit of 6400 to reach that value, it would need to have a CAS of 27.
But this is only one timming. And not even the most important.
Ssateneth
Thats not fair. You are comparing JEDEC to XMP. Compare JEDEC to JEDEC please with no overclock. Also, this aida is old (build 5600, most recent is 5700). An even newer build will probably come out to fix certain issues with the benchmark,
waltc3
And so....when's it going to ship? That's the question for Intel atm.
JamesSneed
To be fair we need to compare whatever can be bought reasonably priced and will run on ADL vs similar price points for DDR4. Using XMP profiles is fair game. JEDEC to JEDEC will make DDR5 look better than real use cases with XMP especially since they stopped at 3200Mt/s for DDR4.
Dazz
CPU Z records the lowest frequency, so i suspect it is recording 4.6Ghz on the little cores while the big cores will be running at 5.3Ghz when doing the single-threaded test and 5Ghz all large core frequency.
P.O.N.
Impressive numbers, latency included. Could ECC have something to do with that?
kanenas
Horus-Anhur
I don't think so.
DDR5 ECC is not what we usually think about ECC.
What we know as ECC, is end to end verification. To make sure the bits are the same, when transferred from memory to CPU.
This tries to detect bit flips, when moving data out of memory. And correct them.
Because this is an end to end ECC, there is a latency cost.
The ECC that is now standard in DDR5 is only on chip.
Because memory cells are becoming smaller and chips more dense, this can cause more bit flips, inside the memory chip.
In this case DDR5 ECC tries to detect and correct bit flips, only inside the chip.
But because this one is done only at the memory, it might not have any additional latency. Or if it does, it will be very small.
This also means that it's possible to use lower quality memory chips that usually would have too many bit flips. So it increases yields for DDR5.
nosirrahx
I know for SODIMM the fastest DDR4 with JEDEC timing is dual rank DDR4 3200 CL20, not sure about desktop RAM though.
https://www.kingston.com/dataSheets/HX432S20IBK2_32.pdf
user1
It might be running at effectively 4t if geardown mode is enabled, in which case it would hit latency pretty badly, It wouldn't be surprising since this would be intel's first memory controller at such high frequencies. not like 10nm is going give intel some free frequency gains this time around.
brogadget
bench screen of my current x299 system (quad-ch.), just for comparison:
Horus-Anhur
I didn't have Intel CPUs, for the last 4 years, so I don't know exactly how settings affect latency.
But I'm guessing that if we tight those timmings, we might see latency go down to the 50s range.
But with the first bios and DDR5 memory ICs, it won't be as low as DDR4 is today.
It might take a couple of years for the tech to mature.
Undying
When haswell-e 5820k lauched as a first ddr4 platform it didnt take years to mature but comfortably beating any ddr3 platform right away. Despite higher latency it had much higher bandwitdh and many architectural improvements over older systems.
Horus-Anhur
I was only talking about latency.
Of course, Alder Lake will have better performance overall, than previous gens.
Dazz
I agree it's been like that with, DDR vs DDR2, DDR2 vs DDR3, DDR3 vs DDR4 so from the patterns it will be the same with DDR4 vs DDR5 the only outlier was EDO (50ns) Vs SDR (20ns) where SDR was much quicker and then again when switching from SDR (20ns) vs DDR (15ns). While raw bandwidth increased, latency has taken more of a hit with each generation. Eventually, it will come down as memory fabrication becomes more mature but latency will never get back to prior generations.
Horus-Anhur
True.
But we must also consider that modern CPUs don't have as much dependency on memory latency, as they once did.
Today's CPUs have much bigger and more complex caches, and more effective OoO, that can mitigate a lot of the issues with memory latency.
To think that today, there are CPUs with more cache than what my first PC had as system memory.....
user1
intel added a 1/2 rate mode for the memory controller in rocket-lake, known as gear2(I mistakenly referred to this as geardown mode), so if you are running 2t + gear 2 , you get effective 4t, combined with increased latency from the slower memory controller, while this is mainly used to reduce power consumption on current chips, it can be presumed that it is necessary to run DDR5 at its intended rate on alderlake, barring some-kind of unexpectedly massive improvement to intel's memory controller.
here is graph from pcgamer showing the effect of gear 2 on performance in f1 2020
[SPOILER]https://cdn.mos.cms.futurecdn.net/94DFxAirogXns7msJYSaa3.png [/SPOILER]
gear2+2t is enough to reduce the performance of a 3200mt/s memory kit, to that of a 2400mt/s kit operating in gear1+t1
its a pretty severe hit to latency.
