Intel's latest development in Advanced Performance Extensions (APX) features the introduction of AVX10, a significant stride forward in providing unified support for AVX-512 on both P-Cores and E-Cores.
This achievement offers solutions to the inherent difficulties associated with the x86 hybrid architecture observed in Alder and Raptor Lake processors. AVX10 equips Intel chips with both E-cores and P-cores to maintain consistent AVX-512 support. P-cores are allocated to run 512-bit instructions exclusively, while 256-bit AVX10 instructions are operable on both P-cores and E-cores, thus delivering comprehensive AVX-512 functionality across the whole chip.
Functioning as an expansion of AVX-512, the AVX10 ISA encapsulates all its features suitable for processors with 256-bit and 512-bit vector register sizes. The consolidated AVX10 ISA comprises AVX-512 vector instructions with an AVX512VL feature flag, a maximum vector register length of 256 bits, alongside eight 32-bit mask registers, and updated versions of 256-bit instructions supporting embedded rounding. P-cores are provided the capacity to handle 512-bit vectors, while E-cores are limited to AVX10's maximum 256-bit vector length.
Applications originally compiled with Intel AVX2 can transition to AVX10 without necessitating extra software adjustments, thereby enhancing performance. Furthermore, E-core-based Intel Xeon processors and Intel products with performance hybrid architecture running highly-threaded vectorizable applications are projected to achieve superior aggregate throughput.
Intel's impending sixth-gen Xeon "Granite Rapids" chips will accommodate AVX10 version 1 (AVX10.1) with 512-bit vector instructions exclusively. Later chips will integrate AVX10.2, which extends support for consolidated 256-bit vector lengths, introduces new AI data types and conversions, enables data movement optimizations, and assures standards support.
Upon AVX10's introduction, Intel will set a freeze on the AVX-512 ISA, and all ensuing AVX-512 instructions will be executed via the AVX10 ISA. Moreover, Intel intends to streamline the AVX10 enumeration methods to alleviate complexity.
The APX announcement by Intel incorporates several enhancements such as 16 extra general-purpose registers, three-operand instruction formats, conditional ISA enhancements, optimized register state save/restore operations, and a fresh 64-bit absolute direct jump instruction. APX is designed to simplify code, elevate register access, and augment CPU efficiency, all while avoiding an impact on the silicon area or power consumption.
This progress in APX and AVX10 comes after Intel's examination into reducing the Intel 64 architecture to an x86 simplified version called x86S.
To access more intricate details about APX and AVX10, refer to the resources provided by Intel at the end of the linked page.
Unified AVX-512 Support via AVX10 on Intel P-Cores and E-Cores
