NVIDIA has announced a major development in computational lithography that will revolutionize the design and manufacture of next-generation chips. The company's new software library, cuLitho, will enable semiconductor leaders like TSMC, Synopsys, and ASML to speed up their manufacturing processes using NVIDIA Hopper architecture GPUs.
With the limits of physics rapidly approaching, this breakthrough technology is poised to change the game in the field of computational lithography. TSMC, the world's leading foundry, and electronic design automation giant, Synopsys, are already integrating the new cuLitho software library into their systems and manufacturing processes. ASML, a major equipment maker, is also working closely with NVIDIA on this project and plans to integrate GPU support into all of its computational lithography software products.
This innovation promises to significantly accelerate the design and production of next-generation chips, positioning NVIDIA at the forefront of the industry's technological advancements. The integration of this software library into existing manufacturing processes will be a game-changer, giving manufacturers a competitive edge in the semiconductor market.
The advance will enable chips with tinier transistors and wires than is now achievable, while accelerating time to market and boosting energy efficiency of the massive data centers that run 24/7 to drive the manufacturing process.
"The chip industry is the foundation of nearly every other industry in the world," said Jensen Huang, founder and CEO of NVIDIA. "With lithography at the limits of physics, NVIDIA's introduction of cuLitho and collaboration with our partners TSMC, ASML and Synopsys allows fabs to increase throughput, reduce their carbon footprint and set the foundation for 2 nm and beyond."
Running on GPUs, cuLitho delivers a performance leap of up to 40x beyond current lithography—the process of creating patterns on a silicon wafer—accelerating the massive computational workloads that currently consume tens of billions of CPU hours every year.
It enables 500 NVIDIA DGX H100 systems to achieve the work of 40,000 CPU systems, running all parts of the computational lithography process in parallel, helping reduce power needs and potential environmental impact.
In the near term, fabs using cuLitho could help produce each day 3-5x more photomasks—the templates for a chip's design—using 9x less power than current configurations. A photomask that required two weeks can now be processed overnight.
Longer term, cuLitho will enable better design rules, higher density, higher yields and AI-powered lithography.
Support From Industry Leaders
NVIDIA is working with key partners to smooth the speedy adoption of these new technologies.
"The cuLitho team has made admirable progress on speeding up computational lithography by moving expensive operations to GPU," said Dr. C.C. Wei, CEO of TSMC. "This development opens up new possibilities for TSMC to deploy lithography solutions like inverse lithography technology and deep learning more broadly in chip manufacturing, making important contributions to the continuation of semiconductor scaling."
"We are planning to integrate support for GPUs into all of our computational lithography software products," said Peter Wennink, CEO of ASML. "Our collaboration with NVIDIA on GPUs and cuLitho should result in tremendous benefit to computational lithography, and therefore to semiconductor scaling. This will be especially true in the era of high NA extreme ultraviolet lithography."
"Computational lithography, specifically optical proximity correction, or OPC, is pushing the boundaries of compute workloads for the most advanced chips," said Aart de Geus, chair and CEO of Synopsys. "By collaborating with our partner NVIDIA to run Synopsys OPC software on the cuLitho platform, we massively accelerated the performance from weeks to days! The team-up of our two leading companies continues to force amazing advances in the industry."
Enabling Semiconductor Scaling
The cost of the computational time needed for the largest workloads in semi manufacturing has in recent years been outpacing Moore's law, due to both the larger number of transistors in newer nodes and more stringent accuracy requirements. Future nodes require more detailed calculations, not all of which can feasibly fit into the available computational bandwidth provided by the current platforms, slowing the pace of innovation in semiconductors.
A fab process change often requires an OPC revision, creating bottlenecks. cuLitho helps remove these bottlenecks, and it makes possible novel solutions and innovative techniques like curvilinear masks, high NA EUV lithography, and sub-atomic photoresist modeling needed for new technology nodes.
