AMD Zen 4 Based Genoa CPUs Get 1 MB L2 Cache per Core
And that's a lot. In Geekbench some scores leaked, and while we don't trust geekbench scores, the specs however are listed in great detail.
AMD Genoa ZEN4 based architecture will find its way into server and workstation CPUs, and thus specs are now leaked to some extent.
An engineering sample CPU is clocked at 1.2 GHz, not relevant since it's an ES sample, but noteworthy is that AMD has increased the L2 cache to 1 MB per core, that double the amount of its predecessor, which is a good thing.
This engineering sample does not appear to feature a 3D V-Cache. It has 128 MB of L3 cache. Even with the clock speed reduced, the Genoa CPU performs remarkably similarly to an EPYC 7513 in single core testing. The EPYC 7513 has a base speed of 2.6 GHz and a boost clock of 3.65 GHz, and it runs Ubuntu 20.04 LTS on both. It outperforms it on several of the subtests, such as navigation, SQLite, and HTML5. Speech recognition and rigid body physics are two areas where it gets close.
This is particularly remarkable given that the Genoa engineering sample operates at less than half the speed of the EPYC 7513. It is possible that it is working at a third of the normal speed. It is anticipated that AMD's Zen 4-based Genoa CPUs will be available later this year. In addition, models with up to 96 cores and 192 threads are envisaged, as well as 12-channel DDR5 memory and PCIe 5.0 expansion capabilities.
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this is cementing AMD's status in Enterprise
and i'm sorry for Intel as they aren't going to get any traction outside of legacy customers with less intensive needs.
software defined feature sets will not cut it against this.
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This would confirm AM5 1MB L2 per core also right?
As far as I know cache is not something that previously has had yield problems, so there should not be any leftover desktop chips with half the cache blocked off, unless they are made on a different production line.
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It's kind of funny seeing how 1MB of L2 is considered large again. I had an old Opteron 180 (socket 939) with 1MB of L2 cache per core. Granted, it didn't have an L3 and only 2 cores.
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Joined: 2017-08-18
This would confirm AM5 1MB L2 per core also right?
As far as I know cache is not something that previously has had yield problems, so there should not be any leftover desktop chips with half the cache blocked off, unless they are made on a different production line.
excellent point.
point of interest is that both Genoa and Ryzen have an spankin' new fab for limited models, and both Genoa and Ryzen (and TR) share fab runs on existing fabs.
the 3D cache models are at maximum output (wafers per month) but only one fab so the lion's share is the Genoa 3D cache and the consumer halo is the 5800X3D, actual numbers of 5800X3D are the just to make the point.
which is also why you might expect the price of the 5800X3D, while the Genoa prices are "a steal".
the main fabs in use have spent the last year pumping out iPhone 13's so volume production is no issue with nothing like 3D cache needing to be dealt with.
AMD has been takin' the cache train for a bit and i don't expect (but don't really know) them to be doing cut-downs there
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Sounds like it will kick ass! Of course it absolutely needs to, considering Intel is back in competition.