AMD Ryzen 7000 8- 12- and 16-core Ryzen CPUs with 3D V-Cache coming?
Earlier on a rumour indocated that only 6 and 8-core Ryzen 7000 processors would get a 3D V-Cache version in 2023. However, a new rumour emerged that there possibly m right be 12 and 16 core versions. We do wonder where AMD would place the 3D V-Cache in the package with so little room and so much heat.
Currently, three sources have confirmed this. It comes as a surprise, nevertheless, that a 6-core 3D v-cache model is not currently in development. This could signal the release of a potential Ryzen 9 7950X3D, Ryzen 9 7900X3D, and Ryzen 7 7700/7800X3D; a Twitter user @harukaze5719 claims that their clock speeds are identical to those of their non-3D counterparts. That would be a step up from the Ryzen 5 5800X3D, which is slower than the 5800X. (3.4 GHz versus 3.8 GHz). It is also reported that the total design power (TDP) of the three X3D-Ryzens is 170 watts. That is on par with the standard 7900X and 7950X in terms of power consumption, but it is a significant increase for the 105-watt Ryzen 7 7700X.
Naturally, these are still just rumours; a reliable source claimed less than three weeks ago that only 6- and 8-core 3d v-cache Ryzens were in development. The announcement likely is January 7, 2023, at CES 2023.
@harukaze5719
They shared 3 exclusive Zen 4 3D info.1) Three Ryzen 7000X3D model is confirmed. 16/12/8C. But about 8C model, it isn't determined model name whether7700X3D or 7800X3D
2) Unlike Zen 3 3D, clock speed will be same or at least almost same.
3) It is expect Jan 23. So CES.
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I think HH concern was towards extra heat generated by adding the cache layer, which we also questioned on the forum when 7k series was launched. As seen on the 5800 3D the heat/surface was really difficult to cool even using high end coolers.
7k is already difficult to keep cool as it is, under heavy loads, I can imagine the 3D Cache version being limited to very expensive custom cooling.
Or it will just throttle and limit the performance based on temperature.
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The IHS for the 7000 series is too thick, so they should just make it thinner in the 3D models, to make room for the 3D cache on top of the chiplets. I'm sure there are technical considerations, but the IHS is still too thick, as made evident by the insane gains from delidding.
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That's a nice spread of CPUs. But no 6 core with 3DV cache. That is a shame, as it would probably be the bang for buck CPU for gamers.
My concern is the TDP. The 5800X3D only has a TFP of 105W, but still, when pushed hard it goes to 95ºC and starts to throttle.
So these new CPUs with 170W of TDP might throttle even harder.
A PBO offset does wonders for the 5800X3D. But for these 7000X3D, it will be essential.
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That doesn't matter; whatever the z-height is of the CCD, the 3D V-Cache version will be the exact same z-height. They have to shave the chiplet down to expose the contact points and when they put the cache on top, it ends up being the exact same height as a normal chiplet.
https://www.anandtech.com/show/16725/amd-demonstrates-stacked-vcache-technology-2-tbsec-for-15-gaming
"The processor with V-Cache is the same z-height as current Zen 3 products - both the core chiplet and the V-Cache are thinned to have an equal z-height as the IOD die for seamless integration"
That's why they have that Structural Silicon; to make sure the top of the chiplet is flat and to help conduct heat. If the current IHS is making contact with the Zen 4 chiplets without the V-Cache, it will have the same contact as the chiplets with V-Cache.
You can confirm this by checking every delid of the 5800X3D; it uses the exact same IHS as the non-X3D chips.
EDIT: Here is a relevant to information about z-heights and heatspreaders from AMD. Information about IHS starts at 1:47 seconds.
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Hilbert, I could be mistaken but from all your comments on the matter I seem to be getting the impression that you think the 3d V-Cache is somehow on a separate die from the CCD, like a chiplet made entirely of cache?
3d V-Cache is actually put directly on a single 8-core CCD by shaving it down then stacking an additional cache layer on top.
Above is a single 8-core chiplet with 3dVcache. There are already contact points on the L3 area of the CCD for them to "add" cache to it, they only need to expose it by shaving the silicon. Then the V-Cache just goes on top and connects via Hybrid Bond 3D*. It doesn't need more space or data lanes than a normal CCD.
The only reason that they didn't release more X3D CPUs on AM4 was because most of the dies were going to Milan-X. (Which, by the way, is also 64 cores, 128 threads, just like a regular non-X Milan CPU)
The X3D chiplets with 3D V-Cache are the same size, shape and contact points and core count as a regular CCD. The only difference between an X3D and a non-X3D chiplet is how much cache they have.
Sorry if you already knew all this, Hilbert. But it kept standing out to me based on your previous comments on this that you seemed to imply that there was need for more lanes or space or something for X3D CPUs.
Please don't be mad at me.
*EDIT: Corrected to Hybrid Bond 3D, it doesn't use TSVs.