AMD Naples 32-core Zen-Processors photos
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Frances
yasamoka
David3k
DLD
I read this, breathless!
@David3k
Wow! You aren't a "member guru'', you're a AncientMahaMaximus Guru here!Thank you, David.
yasamoka
Stairmand
"Never bent CPU socket pins on a motherboard before?"
No I haven't because I'm not an idiot. You must be pretty ham-fisted to do that.
yasamoka
KissSh0t
I've bent cpu pins on the cpu before!
Fixed it though..... through pure sweat and tears.....
Broke a ram stick too trying to plug it in, since then I hate ram sticks with tall cooling units.
OCZ Never Again.
*stares off into the distance*
tsunami231
PrMinisterGR
http://imgur.com/mO4esKx.jpg
Another tidbit I found very interesting is this one:
It seems that the CPU's "internal" language is not that far away from x86 itself, which is actually quite peculiar.
Another little peculiarity, linked to the L3 discussion above:
I know that the fabric that connects multiple cores is different than an interposer that can take HBM, but I bet that the design of having an out-of-the-CPU memory as LLC was on purpose so that something between the processor complex and RAM can be used. I won't be surprised to see Zen CPUs with HBM on, it sounds almost like a drop in solution.
The L3 is shared between each four Zen cores. Unlike Intel, it's not shared with all cores in a CPU. This sounds "bad", until you see that the Intel design is using a 2MB/core design and it's connecting to those 8 cores using 16-way associativity. Zen cores get 2MB/core, but they get 16-way associativity per 4 cores. In ideal situations that could translate for up to 80% lower latency in cache access, in addition to that cache being a victim cache. The L2 is also double the size vs Skylake (512kb vs 256kb) and it has double the associativity (8-way vs 4-way). The L3 and the whole physical design is made in a way that all the cores have the same average latency when "talking" to the L3.
icedman
Amx85
:3eyes:
I can´t think in 180w of TDP since its base frequency... i expect between 125-140w, and other thing, they don´t have 512MB lv3 cache, since start we saw, Zen design talks about 1MB per Thread or 2MB per Core, Desktop Zen will have total of 16MB lv3 cache on the 8 Core model, each complex (4 Cores) has 8MB lv3, then... Zen´s Opteron has a total of 80MB Cache (64MB lv3 + 16MB lv2 caches) per CPU
chispy
I wonder if this cpus will be overclockable , at least to 3.8Ghz~4.0Ghz would be nice.
schmidtbag
chispy
Athlonite