PCI-SIG is excited to disclose that the first review draft of the PCI Express (PCIe) 7.0 specification, version 0.3, is now accessible to its members.
This significant milestone signifies the completion of the initial review draft and its subsequent approval by the work group. It demonstrates PCI-SIG's commitment to meeting the planned release of the full specification in 2025.
The PCIe 7.0 specification is specifically designed to cater to the growing demands of emerging applications such as 800 G Ethernet, AI/ML, Cloud, and Quantum Computing. Furthermore, it targets data-intensive markets, including Hyperscale Data Centers, High-Performance Computing (HPC), Edge Computing, and Military/Aerospace.
Key Objectives of the PCIe 7.0 Specification:
- Achieving a data rate of 128 GT/s and facilitating a bi-directional throughput of up to 512 GB/s in an x16 configuration.
- Implementation of PAM4 signaling for improved data transmission.
- Definition of channel parameters for enhanced performance.
- Ensuring low-latency and high-reliability features.
- Enhancing power efficiency.
- Ensuring backward compatibility with all previous generations of PCIe technology.
PCI-SIG's specification development process, which has evolved over the course of three decades, continues to guide the organization towards success. The unwavering dedication and diligent efforts of our work groups have positioned PCI-SIG at the forefront of delivering a high-bandwidth, low-latency interconnect for emerging markets.
PCI-SIG Availability of PCIe 7.0 Specification, Version 0.3 - 512 GB/s through x16-slot by 2027
