Intel to fab Meteor Lake Die on Intel 4 Node / 20% higher clocks

Intel has next level and gen Intel 4-chip technology in the works, Meteror Lake CPU clock rates will be are 20+% faster while keeping the same TDPs. Intel 4 is the first chip node where euv chip machines are used. Intel also demonstrated a dieshot of a Meteor Lake processor.

Intel revealed at the IEEE VLSI Symposium 2022 that Intel 4 allows 21.5 percent higher clock speeds at the same tdp, 40 percent lower energy consumption at the same clock speeds, or a combination thereof. Tom's Hardware discusses the presentation in an article.

Intel is creating many nodes concurrently in order to meet its promise of delivering five nodes in four years, and Intel 4 is the second step in that journey. Let's start with a closer look at the Meteor Lake die, then get into the specifics of the I4 presentation. Meteor Lake from Intel will be the first product to use the I4 technology. Meteor Lake is expected to be released in 2023, according to Intel. Meteor Lake will employ Intel's 3D stacking packaging technology, as seen with Lakefield chips. This will, however, be Intel's first step into high-volume manufacturing with this cutting-edge packaging technology.

TSV connectors will be used to connect the four die (referred to as 'tiles' in Intel nomenclature) to an interposer. Intel has not revealed whether this interposer will be active or passive, or whether it will house caches or other control circuits. The computing tile, I/O tile, SOC tile, and graphics tile will be mounted on this interposer by Intel. Intel has stated that the computation tile will use I4, but has not indicated which nodes would be used for the remaining tiles. TSMC's N3 (3nm) node with the Meteor and Arrow Lake CPUs was listed on a slide in the above album during the company's Analyst Day earlier this year. This is often assumed to be the graphical tile. Only time will tell.

Meteor Lake chips, like Alder Lake, have an x86 hybrid architecture. We have six p-cores and eight e-cores in this example. On the left of the compute die, we can see six blue-colored Redwood Cove performance cores (p-cores), which are used for latency- and performance-sensitive operations. On the right, we observe two purple four-core clusters of Crestmont efficiency cores (e-cores). Background and multi-threaded work are handled by these cores. The L3 caches and connectivity circuitry are located in the chip's core. Intel has yet to provide a further description of the differences between the SoC and I/O tiles, with the former a likely candidate for memory controllers and PCIe interfaces, while the latter could be for Thunderbolt and other PCH-types of interfaces. Because the I4 node is forward compatible with the I3, designs can be switched between the two without going through the time-consuming porting process. Intel claims that the I4's successor, dubbed 'Intel 3,' will include both high-performance and high-density libraries. To further simplify the design, the I3 process will include improved transistors and interconnects, as well as more EUV layers. The I3 node will be 18% quicker than the I4 node and will be the first new node offered by Intel through Intel Foundry Services (IFS) (the company already offers its existing 16nm).