Intel LGA 7529 Processors are Nearly 10cm in Length

#6116282 Posted on: 03/28/2023 02:43 PM

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I feel like there must be an upper limit to how many pins are actually needed. You need a finite amount to handle the PCIe lanes and memory channels; there's not really a point in having more than 128 PCIe lanes (unless you're doing something like AMD where you're linking the CPUs via PCIe) and there gets to be a point where you just simply can't fit all the traces on a motherboard for more memory channels. With how large these packages are, it makes sense to integrate more onto the SoC, thereby reducing the need of more pins leading elsewhere to the motherboard.
So unless I'm missing something here, that just leaves pins for power delivery. If 7529 becomes that huge just so all the cores can be fed more power, that's a rather bleak future. Perhaps Intel is intending to compete with AMD by having one gargantuan socket rather than multi-socket designs, which overall makes sense.

#6116322 Posted on: 03/28/2023 03:43 PM

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Considering the large CPUs are MCM based, the chips themselves already are sitting on a substrate. It seems to me the substrate wouldn't be that much thicker to handle the power distribution from far fewer outside points. At the end of the day, though, that would only make the outside of the CPU and the socket on the mobo more safe from external damage, as with the current tech, internally the CPU chiplets would still need that many points of power delivery via the substrate. Still, it would be nicer for anyone assembling a system.

#6116794 Posted on: 03/29/2023 04:31 PM

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I feel like there must be an upper limit to how many pins are actually needed. You need a finite amount to handle the PCIe lanes and memory channels; there's not really a point in having more than 128 PCIe lanes (unless you're doing something like AMD where you're linking the CPUs via PCIe) and there gets to be a point where you just simply can't fit all the traces on a motherboard for more memory channels. With how large these packages are, it makes sense to integrate more onto the SoC, thereby reducing the need of more pins leading elsewhere to the motherboard.
So unless I'm missing something here, that just leaves pins for power delivery. If 7529 becomes that huge just so all the cores can be fed more power, that's a rather bleak future. Perhaps Intel is intending to compete with AMD by having one gargantuan socket rather than multi-socket designs, which overall makes sense.
there are chips that are almost an entire wafer in size, and 128lanes of pcie is really no where near the maximum useful amount, bigger cpus mean more cores per rack , more cores per data center, bigger packages are the logical thing to do when die shrinks do not offer cost reductions and density increases you need to meet demands. you can do more pcb layers, so really there isnt any limit for that so far as you have the cash to pay for it. it is completely possible to have packages tbe size of a dinner plate or larger, it just a matter of cost and application.

#6116865 Posted on: 03/29/2023 07:59 PM

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Do you have an example of one of such chips? I can't imagine how that's done beyond some very niche applications, and likely using some rather large node.
Intel I think still uses UPI links to do inter-socket communication rather than PCIe, which means they have a much lower dependency on PCIe lanes than AMD. Regardless, most server motherboards from what I've seen barely have enough room for 64 lanes of PCIe expansion cards. Granted, a lot of such boards use a lot of their available lanes for things like integrated networking, but my point is: I haven't got the impression there's a demand for more lanes, but rather, faster lanes. So, I still don't see having more than 128 lanes being necessary any time soon, if ever.
There's really only 2 outcomes when it comes to scaling up a processor to such extreme levels:
A. The SoC is so powerful/capable that it reduces how much bandwidth it needs.
B. The demand is so immense that it completely dwarfs the SoC's potential, where it's probably be more cost effective to buy more servers of less potential.
It seems to me there's an upper limit to how much you can cram on a motherboard until it doesn't make economic sense. Since chiplets are basically just more tightly integrated multi-socket designs, I don't really see the purpose in having one gargantuan socket the size of an ITX motherboard with a PCB so thick you would need different chassis standoffs to mount it. By having multiple sockets, you reduce the cost of the package and you can cram more features on the motherboard since you don't have thousands of traces going to one spot.

#6116917 Posted on: 03/29/2023 10:30 PM

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Do you have an example of one of such chips? I can't imagine how that's done beyond some very niche applications, and likely using some rather large node.
Intel I think still uses UPI links to do inter-socket communication rather than PCIe, which means they have a much lower dependency on PCIe lanes than AMD. Regardless, most server motherboards from what I've seen barely have enough room for 64 lanes of PCIe expansion cards. Granted, a lot of such boards use a lot of their available lanes for things like integrated networking, but my point is: I haven't got the impression there's a demand for more lanes, but rather, faster lanes. So, I still don't see having more than 128 lanes being necessary any time soon, if ever.
There's really only 2 outcomes when it comes to scaling up a processor to such extreme levels:
A. The SoC is so powerful/capable that it reduces how much bandwidth it needs.
B. The demand is so immense that it completely dwarfs the SoC's potential, where it's probably be more cost effective to buy more servers of less potential.
It seems to me there's an upper limit to how much you can cram on a motherboard until it doesn't make economic sense. Since chiplets are basically just more tightly integrated multi-socket designs, I don't really see the purpose in having one gargantuan socket the size of an ITX motherboard with a PCB so thick you would need different chassis standoffs to mount it. By having multiple sockets, you reduce the cost of the package and you can cram more features on the motherboard since you don't have thousands of traces going to one spot.
here is the chip https://www.cerebras.net/blog/wafer-scale-processors-the-time-has-come/,(((wafer-scale)))
there is always room for more i/o, and more cores = more i/o. if amd could double the core count per package , they could double the io easily, you don't see much more than 16 layer pcbs on consumer hardware, but you can go beyond 24 layers, There is a long way to go before such things become impractical. If you're building a supremely large cluster or run a data center, more per rack means more throughput, at the current time there is practically infinite demand for computing resources, $30K racks aren't rare when a single xeon can set you back $10-20k, even something like a 24+ layer pcb is going to be a minor cost compared to the rest of the components, if you just think about a single compute node , which may comprise of 2 genoa cpus, and 12 gpus, the total silicon on that is huge, if you can wrap as much as you can into fewer larger packages, that saves you space, circuitry, and cooling complexity. its the obvious solution. and You should see some of the truly enormous mainframes from the past.

check this package out ,

computers were really big before stuff got small. and now due to technical limitations of shrinks, we're going big again. we've been kind of spoiled by node shrinks delivering performance uplift.

Industrial/commercial/government applications have very different requirements compared comsumer. and those giant xeons aren't for consumers, market conditions can support(and have supported) much larger packages.