Intel and Micron Announces Industry First QLC 3D NAND

by Hilbert Hagedoorn on: 05/22/2018 07:48 AM | source: | 5 comment(s)

Intel and Micron announced the production and shipment of the industry’s first 4 bits per cell, or QLC, 3D NAND technology. Intel has begun sampling QLC 3D NAND with select customers and will have product news later this summer. Leveraging a 64-layer structure, the new 4 bits per cell NAND technology achieves 1 terabit (Tb) density per die.

The companies also announced development progress on the third-generation 96-tier 3D NAND structure, providing a 50 percent increase in layers. These advancements in the cell structure continue the companies’ leadership in producing the world’s highest Gb/mm2 areal density.

Both NAND technology advancements—the 64-layer QLC and 96-layer TLC technologies—utilize CMOS under the array (CuA) technology to reduce die sizes and deliver improved performance when compared to competitive approaches. By leveraging four planes vs the competitors’ two planes, the new Intel and Micron NAND flash memory can write and read more cells in parallel, which delivers faster throughput and higher bandwidth at the system level.

The new 64-layer 4bits/cell NAND technology enables denser storage in a smaller space, bringing significant cost savings for read-intensive cloud workloads. It is also well-suited for consumer and client computing applications, providing cost-optimized storage solutions.

Announce Qualification of Industry’s First 4 bits/cell 3D NAND and the Development of 96-Layer 3D NAND Structure

News Highlights

Intel-Micron delivers the 1^st commercially available 1Tb - 4bits/cell (QLC) die in the history of semiconductors
Qualification of 4bits/cell 3D NAND on 64 layer 2^nd Gen 3D NAND has been completed. 4bits/cell (QLC) provides 33% higher density compared to 3bits/cell (TLC)
3^rd Generation 3D NAND uses 96 layers to maintain cost/density leadership
3^RD Generation 3D NAND enables the industry’s highest Gb/mm2 areal density

BOISE, Idaho and SANTA CLARA, Calif., May 21, 2018 - Micron Technology, Inc. (Nasdaq: MU), and Intel Corporation today announced production and shipment of the industry’s first 4bits/cell 3D NAND technology. Leveraging a proven 64-layer structure, the new 4bits/cell NAND technology achieves 1 terabit (Tb) density per die, the world's highest-density flash memory.

Both NAND technology advancements—the 64-layer QLC and 96-layer TLC technologies —utilize CMOS under the array (CuA) technology to reduce die sizes and deliver improved performance when compared to competitive approaches. By leveraging four planes vs the competitors’ two planes, the new Intel and Micron NAND flash memory can write and read more cells in parallel, which delivers faster throughput and higher bandwidth at the system level.

-layer 4bits/cell NAND technology, we are achieving 33 percent higher array density compared to TLC, which enables us to produce the first commercially available 1 terabit die in the history of semiconductors," said Micron Executive Vice President, Technology Development, Scott DeBoer. "We’re continuing flash technology innovation with our 96-layer structure, condensing even more data into smaller spaces, unlocking the possibilities of workload capability and application construction."

“Commercialization of 1Tb 4bits/cell is a big milestone in NVM history and is made possible by numerous innovations in technology and design that further extend the capability of our Floating Gate 3D NAND technology,” said RV Giridhar, Intel vice president, Non-Volatile Memory Technology Development. “The move to 4bits/cell enables compelling new operating points for density and cost in Datacenter and Client storage.”

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ObscureangelPT
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#5548949 Posted on: 05/22/2018 09:08 AM

The biggest question of this qlc ssds are how many writes they can handle until they go under

Hilbert Hagedoorn
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#5548954 Posted on: 05/22/2018 09:24 AM

The biggest question of this qlc ssds are how many writes they can handle until they go under

TLC writes 3-bits per cell, with a claimed 1000 P/E cycles. QLC will write 4-bits per cell, and the interesting fact here, it'll do the same 1000 P/E cycles according to Toshiba at the time. The theory is that the NAND cell is a little bit bigger to compensate on that. Add to that improved wearing techniques and such. Time will tell though, but everybody HATED the move from SLC to MLC, then shortly thereafter TLC was the black sheep, which now has become a very proper and trustworthy NAND series. I guess It'll be the same with QLC in the beginning.

Kaarme
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#5548968 Posted on: 05/22/2018 09:59 AM

Time will tell though, but everybody HATED the move from SLC to MLC, then shortly thereafter TLC was the black sheep, which now has become a very proper and trustworthy NAND series. I guess It'll be the same with QLC in the beginning.

If you consider the nomenclature, it's quite interesting that two bits per cell is already called multi-level cell, MLC. It's as if back when it was invented, the industry thought: "That's it". So, it was just the original SLC and then the MLC, single and multi. If they had already foreseen in the more distant future there would be triple bits per cell followed by quad bits per cell, the name for the two bits per cell wouldn't have been multi, it woud be have been double, dual, or something like it. What I am saying is that if the industry itself, the one making money out of this, thought two is already the ultimate form, then surely nobody can be blamed for being suspicious when the cell is divided to more and more levels.

Silva
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#5549033 Posted on: 05/22/2018 12:59 PM

When SLC was a norm I too hated the move on MLC because it meant you'd lose life on the SSD. But because SLC was so expensive, I would never be able to buy one.
In the end, I was grateful for MLC and bought an SSD born from this tech. I'm really happy with it and averaging 12Gb per day it will take well over a decade for it to die on me from wear.
That said, with the memory prices going up and people wanting more density (to compete with HDD), they had to find a way to create more density. What better way to repeat what they already knew?
It was great people hated on the tech because that way they made sure the reliability stayed the same (bigger cells) and I'm sure we will see more in the future: 5-bit per cell, 6-bit per cell, etc.
And it will be fine, as long as they keep the 1000 or more P/E cycles.

Venix
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#5549063 Posted on: 05/22/2018 02:14 PM

when you talk about 2++ tb drives .... every P/E cycle should last longer no ? especially if you make this a steam library drive ! so ... in a way if they make a QLC 2tb for 100-150 euros and rate it even on 300 P/E i would personally buy one to make it my steam drive !

also to that note so far everyone that did test on ssd's life every time the tested drives way passed their p/e cycles before they die out no ? i think the ratting they give is the worst case scenario / luck

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