AMD joins consortium for CXL interconnect based on pci-e 5.0

AMD joins the Compute Express Link consortium, which is developing an interconnect based on the PCIe 5.0 interface. AMD follows with Intel and Arm

Compute Express Link (CXL) is an open industry standard interconnect offering high-bandwidth, low-latency connectivity between host processors, systems and devices such as accelerator cards, memory buffers, and smart I/O devices. Designed to address the increasing demands of high-performance computational workloads, CXL targets heterogeneous processing and memory systems across a range of high-performance computing applications by enabling coherency and memory semantics between processors and systems. This is increasingly important as processing data in Artificial Intelligence and Machine Learning requires a diverse mix of scalar, vector, matrix and spatial architectures across a range of accelerator options.

Since 2016 AMD has played a leadership role in driving three other new bus/interconnect standards, CCIX, OpenCAPI and Gen-Z. Like CXL, these three efforts are driven by the need to create tighter coupling and coherency between processors and accelerators, and better exploit new and emerging memory/storage technologies in open, standards-based solutions.

While these different groups have been working to solve similar problems, each approach has its differences. As a long-standing supporter of open standards, we’re excited to join CXL and the possibilities presented as we work with other ecosystem leaders to address challenges we face as an industry.