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Guru3D.com » News » AMD joins consortium for CXL interconnect based on pci-e 5.0

AMD joins consortium for CXL interconnect based on pci-e 5.0

by Hilbert Hagedoorn on: 07/19/2019 01:46 PM | source: | 6 comment(s)
AMD joins consortium for CXL interconnect based on pci-e 5.0

AMD joins the Compute Express Link consortium, which is developing an interconnect based on the PCIe 5.0 interface. AMD follows with Intel and Arm

Compute Express Link (CXL) is an open industry standard interconnect offering high-bandwidth, low-latency connectivity between host processors, systems and devices such as accelerator cards, memory buffers, and smart I/O devices. Designed to address the increasing demands of high-performance computational workloads, CXL targets heterogeneous processing and memory systems across a range of high-performance computing applications by enabling coherency and memory semantics between processors and systems. This is increasingly important as processing data in Artificial Intelligence and Machine Learning requires a diverse mix of scalar, vector, matrix and spatial architectures across a range of accelerator options.

Since 2016 AMD has played a leadership role in driving three other new bus/interconnect standards, CCIX, OpenCAPI and Gen-Z. Like CXL, these three efforts are driven by the need to create tighter coupling and coherency between processors and accelerators, and better exploit new and emerging memory/storage technologies in open, standards-based solutions.

While these different groups have been working to solve similar problems, each approach has its differences. As a long-standing supporter of open standards, we’re excited to join CXL and the possibilities presented as we work with other ecosystem leaders to address challenges we face as an industry.







« Review: AMD Ryzen 5 3600X Six core processor · AMD joins consortium for CXL interconnect based on pci-e 5.0 · GeForce RTX 2080 Super Spotted in FF XV Benchmark - 8% faster »

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Clawedge
Senior Member



Posts: 2599
Joined: 2006-09-02

#5692702 Posted on: 07/19/2019 11:02 PM
This is cool, I hope the industry also moved to a similar protocol for peripheral devices

Fox2232
Senior Member



Posts: 11809
Joined: 2012-07-20

#5692780 Posted on: 07/20/2019 07:25 AM
It is continuation of their long lasting push towards HSA.
Members of CXL.

I wonder if nVidia continues to push proprietary tech or joins in.

Zhyr
Member



Posts: 48
Joined: 2002-06-22

#5693213 Posted on: 07/22/2019 10:57 AM
If only someone would come up with a Universal Serial Bus that we could call USB....

Alessio1989
Senior Member



Posts: 2269
Joined: 2015-06-11

#5693222 Posted on: 07/22/2019 11:43 AM
How much would those latencies lower compared to traditional PCI-E implementation?

Venix
Senior Member



Posts: 2404
Joined: 2016-08-01

#5693479 Posted on: 07/23/2019 03:49 AM
How much would those latencies lower compared to traditional PCI-E implementation?


I think they are still in the process of "the lower the better" we can't know before some first samples can we ?

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