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AMD Flirting with big.LITTLE processor design - files a Patent
You know it for them recent Intel rumours, processors with a couple of energy-friendly cores, and then some huge ones for heavy-duty processing. It seems to be something that AMD wants to explore as well, as they filed a patent for it.
Much like Intel Lakefield, the small cores deal with light tasks more energy-efficiently, while the large cores are better suited for the heavy work. The patent shows a schematic of a theoretical chip with two groups of cores. Both the large and small cores have their own cache, the next cache level share the two types of cores. The design here is interesting as for some usage the operating system is not needed into the mix, the processor itself could make decisions on what to run where. Also, these do not necessarily need to be CPU cores, GPU cores can also be used as well. That makes this complicated but usability, extremely large.
The patent request appears to be still in an early phase, information and designs thus can change. Also, it's a patent, so it's not a sure thing hat a design likely this will ever see make it into the real world. But interesting it is, as AMD is eying that big LITTLE concept.
Fediuld
Senior Member
Posts: 523
Joined: 2016-10-04
Senior Member
Posts: 523
Joined: 2016-10-04
#5816605 Posted on: 08/10/2020 11:54 AM
One should distinct instructions used. That "small" CPU core may happen to be faster at certain workloads. It can as well be some minimalistic CPU with extra fixed function HW for some things that would make logic in larger Zen core too slow.
What it can be missing? AVX?
What is the point of AVX512? Everyone writing code for ML where could have some use, they write code for GPUs either CUDA/Tensor or through RoCm for GCN (and upcoming CDNA). They do not write for CPUs let alone customised code for AVX 512 which would run on what? 28 core CPUs when can buy 64 core CPU for less and don't care about AVX 512 extra performance since the brute force is enough?
So let AVX 512 die. Is useless pile of crap.
One should distinct instructions used. That "small" CPU core may happen to be faster at certain workloads. It can as well be some minimalistic CPU with extra fixed function HW for some things that would make logic in larger Zen core too slow.
What it can be missing? AVX?
What is the point of AVX512? Everyone writing code for ML where could have some use, they write code for GPUs either CUDA/Tensor or through RoCm for GCN (and upcoming CDNA). They do not write for CPUs let alone customised code for AVX 512 which would run on what? 28 core CPUs when can buy 64 core CPU for less and don't care about AVX 512 extra performance since the brute force is enough?
So let AVX 512 die. Is useless pile of crap.
Denial
Senior Member
Posts: 13233
Joined: 2004-05-16
Senior Member
Posts: 13233
Joined: 2004-05-16
#5816617 Posted on: 08/10/2020 12:53 PM
What is the point of AVX512? Everyone writing code for ML where could have some use, they write code for GPUs either CUDA/Tensor or through RoCm for GCN (and upcoming CDNA). They do not write for CPUs let alone customised code for AVX 512 which would run on what? 28 core CPUs when can buy 64 core CPU for less and don't care about AVX 512 extra performance since the brute force is enough?
So let AVX 512 die. Is useless pile of crap.
Ya, opmask and scatter totally a useless pile of crap. I remember my first joke.
What is the point of AVX512? Everyone writing code for ML where could have some use, they write code for GPUs either CUDA/Tensor or through RoCm for GCN (and upcoming CDNA). They do not write for CPUs let alone customised code for AVX 512 which would run on what? 28 core CPUs when can buy 64 core CPU for less and don't care about AVX 512 extra performance since the brute force is enough?
So let AVX 512 die. Is useless pile of crap.
Ya, opmask and scatter totally a useless pile of crap. I remember my first joke.
JamesSneed
Senior Member
Posts: 1110
Joined: 2017-02-14
Senior Member
Posts: 1110
Joined: 2017-02-14
#5816644 Posted on: 08/10/2020 02:18 PM
This whole hybrid computing(its not big.little that is ARM specific term) is pointless unless you are severely TDP constrained think tables or smaller. You are simply one full node of process improvement away from having all large cores anyhow. The SoC fragmentation this causes is going to be a complete pain especially if everyone does there own hybrid computing approach. I have no doubt Microsoft would screw up the kernel trying to deal with these differences. I'm not a fan of this at all. For example we will see Intel's Tiger Lake get dominated by AMD's next gen APU's in 2021 because of the better process and all large cores.
This whole hybrid computing(its not big.little that is ARM specific term) is pointless unless you are severely TDP constrained think tables or smaller. You are simply one full node of process improvement away from having all large cores anyhow. The SoC fragmentation this causes is going to be a complete pain especially if everyone does there own hybrid computing approach. I have no doubt Microsoft would screw up the kernel trying to deal with these differences. I'm not a fan of this at all. For example we will see Intel's Tiger Lake get dominated by AMD's next gen APU's in 2021 because of the better process and all large cores.
schmidtbag
Senior Member
Posts: 5582
Joined: 2012-11-10
Senior Member
Posts: 5582
Joined: 2012-11-10
#5816648 Posted on: 08/10/2020 02:56 PM
Yes! I'm glad AMD is doing this too, though I'm a little surprised Intel hasn't patented this in a way to cripple AMD's efforts, since Intel also appears to be going this route.
One should distinct instructions used. That "small" CPU core may happen to be faster at certain workloads. It can as well be some minimalistic CPU with extra fixed function HW for some things that would make logic in larger Zen core too slow.
What it can be missing? AVX?
Yes, I'm thinking the smaller cores will probably be able to clock faster for tasks that need it, while also sipping power for background workloads.
There's plenty they could strip out. Just look at ARM - its instruction set is pretty sparse yet you can comfortably run a laptop experience on it, provided you have about 8 cores.
I figure most calculations are pretty basic and don't need any fancy instructions.
This whole hybrid computing(its not big.little that is ARM specific term) is pointless unless you are severely TDP constrained think tables or smaller. You are simply one full node of process improvement away from having all large cores anyhow. The SoC fragmentation this causes is going to be a complete pain especially if everyone does there own hybrid computing approach. I have no doubt Microsoft would screw up the kernel trying to deal with these differences. I'm not a fan of this at all. For example we will see Intel's Tiger Lake get dominated by AMD's next gen APU's in 2021 because of the better process and all large cores.
I agree it is a problem if everyone's approach is a little too different, but I don't think you're looking at this the right way. TDP issues are why x86 has been unable to compete in the mobile market, and isn't too favorable in the robotics market either. For desktops, I imagine the small cores could be clocked significantly higher, so if you're running a simple workload, adding more instructions doesn't accomplish anything; it just makes the chip more expensive and less stable at higher speeds. So in a performance standpoint, these could be very useful.
Meanwhile, if something doesn't demand too many "fancy instructions" but can utilize many cores, you can fit more of the small cores on a single die. So depending on your workload, you could get a significant performance uplift at a lower cost and lower wattage.
Yes! I'm glad AMD is doing this too, though I'm a little surprised Intel hasn't patented this in a way to cripple AMD's efforts, since Intel also appears to be going this route.
One should distinct instructions used. That "small" CPU core may happen to be faster at certain workloads. It can as well be some minimalistic CPU with extra fixed function HW for some things that would make logic in larger Zen core too slow.
What it can be missing? AVX?
Yes, I'm thinking the smaller cores will probably be able to clock faster for tasks that need it, while also sipping power for background workloads.
There's plenty they could strip out. Just look at ARM - its instruction set is pretty sparse yet you can comfortably run a laptop experience on it, provided you have about 8 cores.
I figure most calculations are pretty basic and don't need any fancy instructions.
This whole hybrid computing(its not big.little that is ARM specific term) is pointless unless you are severely TDP constrained think tables or smaller. You are simply one full node of process improvement away from having all large cores anyhow. The SoC fragmentation this causes is going to be a complete pain especially if everyone does there own hybrid computing approach. I have no doubt Microsoft would screw up the kernel trying to deal with these differences. I'm not a fan of this at all. For example we will see Intel's Tiger Lake get dominated by AMD's next gen APU's in 2021 because of the better process and all large cores.
I agree it is a problem if everyone's approach is a little too different, but I don't think you're looking at this the right way. TDP issues are why x86 has been unable to compete in the mobile market, and isn't too favorable in the robotics market either. For desktops, I imagine the small cores could be clocked significantly higher, so if you're running a simple workload, adding more instructions doesn't accomplish anything; it just makes the chip more expensive and less stable at higher speeds. So in a performance standpoint, these could be very useful.
Meanwhile, if something doesn't demand too many "fancy instructions" but can utilize many cores, you can fit more of the small cores on a single die. So depending on your workload, you could get a significant performance uplift at a lower cost and lower wattage.
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One should distinct instructions used. That "small" CPU core may happen to be faster at certain workloads. It can as well be some minimalistic CPU with extra fixed function HW for some things that would make logic in larger Zen core too slow.
What it can be missing? AVX?