Aiming to enhance read/write performance and capacity, engineers from both firms are working on the development of 8-plane 3D NAND devices and 3D NAND ICs with over 300 layers.
Kioxia, in collaboration with its manufacturing partner Western Digital, is gearing up to showcase their cutting-edge innovations in 3D NAND memory devices at the 2023 Symposium on VLSI Technology and Circuits. Kioxia will introduce a paper outlining its eight-plane 1Tb 3D TLC NAND device featuring over 210 active layers and a 3.2 GT/s interface. This groundbreaking device boasts a read latency of a mere 40 μs and a program throughput of 205 MB/s. Kioxia's innovative one-pulse-two-strobe method and hybrid row address decoders help tackle wiring congestion, resulting in reduced sensing time and accelerated data transfer.
Additionally, the companies are progressing in the development of 3D NAND devices with over 300 active word layers, utilizing Metal Induced Lateral Crystallization (MILC) techniques. Employing nickel gettering and other state-of-the-art approaches, this 3D NAND IC has managed to decrease read noise by at least 40% and amplify channel conductance tenfold without compromising cell reliability.
Tokyo Electron, a wafer fab equipment manufacturer, will exhibit its High-Aspect-Ratio (HAR) dielectric etching technology, which enables the fabrication of 400-layer 3D NAND nodes with over 10-micron vertical channels in just 33 minutes, while reducing the carbon footprint by 84%.