Intel Xeon E5 Sandy Bridge-E CPUs Launch Schedule

At this year's IDF conference, Intel made public the fact that it has delayed the arrival of its first Xeon E5 server processors, but nobody back then knew when these CPUs will arrive. A recent report however has managed to uncover the chip maker's plans regarding this new series of CPUs as SoftPedia reports today:

Previously, the Xeon E5 product families were scheduled for a Q4 2011 release, but CPU World has find out that Intel's current roadmaps place the launch of these chips in the second Q1 of 2012.

Just as their naming scheme implies, Xeon E5-1600 CPUs are to be installed in uni-processor machines while products in the Xeon E5-2600 range support dual-socket configurations.

Despite this difference, both of these Xeon CPU series will be compatible with Intel's socket R motherboards (LGA-2011).

Just like their desktop counterparts, the CPUs released in the Xeon 2600-series will feature HyperThreading, Turbo Boost technology, as well as the AVX and AES instructions, but they will also receive support for VT-x / VT-d / VT-c virtualization.

Next to the Xeon E5-2600 series, Intel also plans to release the Xeon E5-2400 processor family which also supports dual-socket systems and is compatible with LGA-1356 motherboards (socket B2).

As the E5-2400 processors will be based on the Sandy Bridge-EN architecture, they carry a tri-channel memory controller, compared to the quad-channel controller available in LGA-2011 chips.

Together with these three processor series, Intel will also introduce a quad-socket version of the Sandy Bridge-EP, dubbed the E5-4600, the launch of which has now been postponed for the second quarter of 2012.

All Xeon E5 processors will use the C600 chipset, code-name Patsburg, that we detailed in a previous report.

Sandy Bridge-EN and Sandy Bridge-EP CPUs feature as much as eight processing cores, pack up to 20MB of shared L3 cache, have a TDP rated between 80W and 150W, and support one or two Quick Path Interconnect links, depending on the model.