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AMD EHP Processor (EHP) has up-to 32 CPU cores and 32GB memory
AMD released information on their Exascale Heterogenous Processor (EHP) for Supercomputers, quite a few words eh ? Basically you 'could' read EHP as APU on a more advanced scale. EHP actually shares similarities with the recently launched Fiji chip with it's interposer and on-die memory.
EHP a die with several components mounted into it in the form of a number of processor cores, then a GPGPU unit all combined with the interposer which bridges the die towards a maximum of 32 GB of HBM2 memory, that would be on-package this on the EHP/APU.
if you combined the CPU/GPU with GPGPU functionality and the heaps of memory bandwidth, you can imagine that would be a pretty powerful solution for super-computing.
It is rumored that the processor side of things will get 32 cores, we think Zen micro-architecture here with eight "Zen" quad-core units. AMD is aiming to release the first engineering sample of this what will be a massive chip by 2016-17.
Bansaku
Senior Member
Posts: 159
Joined: 2009-08-20
Senior Member
Posts: 159
Joined: 2009-08-20
#5134882 Posted on: 08/03/2015 10:15 AM
Until you see the power bill!
Sounds awesome!
Until you see the power bill!
Lane
Senior Member
Posts: 6361
Joined: 2005-02-25
Senior Member
Posts: 6361
Joined: 2005-02-25
#5134888 Posted on: 08/03/2015 10:27 AM
This "thing" is made for attain the ExaFlops ( 1000 Petaflops ), for supercomputers, today supercomputers achieve at best 50 PetaFlops.
The question in reality is not much this APU, this was a design example, the thing is how they can combine it in a system for achieve it. This was point of the presentation for IEEE.
Here's the original image with the explanation about the off chips memory package, the cabinet network ..etc .
Until you see the power bill!
This "thing" is made for attain the ExaFlops ( 1000 Petaflops ), for supercomputers, today supercomputers achieve at best 50 PetaFlops.
The question in reality is not much this APU, this was a design example, the thing is how they can combine it in a system for achieve it. This was point of the presentation for IEEE.
Here's the original image with the explanation about the off chips memory package, the cabinet network ..etc .
rl66
Senior Member
Posts: 3433
Joined: 2007-05-31
Senior Member
Posts: 3433
Joined: 2007-05-31
#5134897 Posted on: 08/03/2015 10:47 AM
after the fiasco of the last 2 gen, AMD should do something really exeptional to just get attention... despite sounding good this doesn't seem exeptional.
after the fiasco of the last 2 gen, AMD should do something really exeptional to just get attention... despite sounding good this doesn't seem exeptional.
Lane
Senior Member
Posts: 6361
Joined: 2005-02-25
Senior Member
Posts: 6361
Joined: 2005-02-25
#5134904 Posted on: 08/03/2015 11:06 AM
You want to buy an ExaFlops supercomputer ?
This thing is not made for desktop, the gpu units surely dont have rop, tmu's, they are just there for computing.
Anyway, the design with HBM2, a gpu cores + a CPU + Nvram should be just enormous even for workstation computing...
after the fiasco of the last 2 gen, AMD should do something really exeptional to just get attention... despite sounding good this doesn't seem exeptional.
You want to buy an ExaFlops supercomputer ?
This thing is not made for desktop, the gpu units surely dont have rop, tmu's, they are just there for computing.
Anyway, the design with HBM2, a gpu cores + a CPU + Nvram should be just enormous even for workstation computing...
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Joined: 2005-02-02
Sounds awesome!