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Guru3D.com » News » Xilinx Announces the VU19P FPGA Featuring 35 billion transistors

Xilinx Announces the VU19P FPGA Featuring 35 billion transistors

by Hilbert Hagedoorn on: 08/28/2019 07:41 AM | source: | 3 comment(s)
Xilinx Announces the VU19P  FPGA Featuring 35 billion transistors

Xilinx announced the expansion of its 16 nanometers (nm) Virtex® UltraScale+ family to now include the world's largest FPGA — the Virtex UltraScale+ VU19P. It contains a whopping 35 billion transistor.

The VU19P provides the highest logic density and I/O count on a single device ever built, enabling emulation and prototyping of tomorrow's most advanced ASIC and SoC technologies, as well as test, measurement, compute, networking, aerospace and defense-related applications.

The VU19P sets a new standard in FPGAs, featuring 9 million system logic cells, up to 1.5 terabits per-second of DDR4 memory bandwidth and up to 4.5 terabits per-second of transceiver bandwidth, and over 2,000 user I/Os. It enables the prototyping and emulation of today's most complex SoCs as well as the development of emerging, complex algorithms such as those used for artificial intelligence, machine learning, video processing and sensor fusion. The VU19P is 1.6X larger than its predecessor and what was previously the industry's largest FPGA — the 20 nm Virtex UltraScale 440 FPGA.  

"The VU19P enables developers to accelerate hardware validation and begin software integration before their ASIC or SoC is available," said Sumit Shah, senior director, product line marketing and management, Xilinx. "This is our third generation of world-record FPGAs. First was the Virtex-7 2000T, followed by the Virtex UltraScale VU440, and now the Virtex UltraScale+ VU19P. But this is more than silicon technology; we're providing robust and proven tool flows and IP to support it."

The VU19P is supported by an extensive set of debug, visibility tools, and IP, providing customers with a comprehensive development platform to quickly design and validate next-generation applications and technologies. Hardware and software co-validation allows for developers to bring up software and implement custom features before physical parts are available. Moreover, the design flow can be co-optimized by using the Xilinx Vivado® Design Suite, which reduces cost and tape-out risk, and improves efficiency and time-to-market.

"Arm relies on Xilinx devices as part of our process for validating our next-generation processor IP and SoC technology," said Tran Nguyen, director of design services, Arm. "The new VU19P will further enable Arm, and many others in our ecosystem, to accelerate the design, development and validation of our most ambitious roadmap technologies."

The VU19P will be generally available in the fall of 2020. To learn more about the VU19P as well as Xilinx's complete line of Virtex UltraScale+ FPGA products, visit www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale-plus-vu19p.html.



Xilinx Announces the VU19P  FPGA Featuring 35 billion transistors




« AMD Settles Bulldozer Core Count Lawsuit for 12 Million - 35 bucks per chip · Xilinx Announces the VU19P FPGA Featuring 35 billion transistors · Download: CPU-Z Version 1.90 adds support for Threadripper 3000 »

geogan
Senior Member



Posts: 798
Joined: 2010-01-04

#5704965 Posted on: 08/28/2019 09:48 AM
I'm afraid to ask but... price?

easytomy
Member



Posts: 51
Joined: 2017-05-08

#5705541 Posted on: 08/29/2019 02:47 PM
Designed to be used in ...?
("a variety of applications" is not a valid answer)

Denial
Senior Member



Posts: 13234
Joined: 2004-05-16

#5705549 Posted on: 08/29/2019 02:59 PM
Designed to be used in ...?
("a variety of applications" is not a valid answer)

It says it in the article.

It's an FPGA for prototyping and validation of design. Basically when a company like ARM goes "we want to try this new architectural thing with our SoCs" - instead of fabbing that chip plus hundreds of others as they work through various iterations and fixes they simulate it on this FPGA.

I'm afraid to ask but... price?

Probably $200-300K but typically you enter a contract with Xilinix because you use their entire software ecosystem when prototyping on stuff like this.

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