TSMC expects 5nm production in 2020
So the story goes like this, we'll see 16, 15 and 14nm solicon this year. Then in two years we'll see 7nm .. and two years later in 2020 we'll be at 5nm ! Man we are running our of scale, so after nanometer we'll enter picometer.
Anyway, TSMC will be ready to roll out its 5nm process technology two years after the launch of its 7nm node. Digitimes reports the following on the topic;
TSMC expects to start production of 7nm chips in the first half of 2018, said company co-CEO Mark Liu at a recent investors meeting. He did not specify whether the node would be ready for volume production or just risk production.
In addition, TSMC has been engaged in R&D for 5nm process technology for one year, said Liu, adding that the node will be ready for launch in the first half of 2020.
TSMC also revealed it will be ready to use extreme ultraviolet (EUV) lithography to make 5nm chips. "We've made significant progress with EUV to prepare for its insertion, likely in 5nm," Liu indicated.
As for 10nm, TSMC expects to qualify the node which will be ready for customer tape-outs in the first quarter of 2016, Liu said.
CC Wei, TSMC's other co-CEO, noted that TSMC's share of the 14/16nm foundry market segment will rise to more than 70% in 2016 from about 40% in 2015. TSMC's 16nm FinFET processes consisting of 16FF (16nm FinFET), 16FF+ (16nm FinFET Plus) and 16FFC (16nm FinFET Compact) will account for more than 20% of the foundry's total wafer revenues in 2016, Wei said.
The new 16nm FFC node, a low-power and low-cost version of TSMC's 16nm FinFET products, will be ready for volume production in the first quarter of 2016, Wei indicated.
Wei also disclosed TSMC is on track to move its integrated fan-out (InFO) wafer-level packaging technology to volume production in the second quarter of 2016. "We do not expect adoption by a large number of customers. However, we do expect a few very large volume customers," Wei said.
Apple is reportedly among the first wave of customers adopting the InFO packaging technology.
Senior Member
Posts: 2218
Joined: 2013-03-10
They don't seem concerned at all, happily talking already about 7 and 5nm, despite the pioneer Intel encountering problems with 10nm.
Senior Member
Posts: 241
Joined: 2005-10-08
But there wasn't a quantum barrier somewhere in this scales (less than 10nm) because there was too few atoms to dope the semiconductor material as type N or P?
Will this be the new TSMC 20nm node?
Senior Member
Posts: 12056
Joined: 2014-07-21
Uhm, maybe it's just me, but do you guys really expect them to have it ready in 2020? Maybe they want to have it, but with low yields we're more likely to see anything with such a small scale being available in small numbers, and then they will sell it to mobile manufacturer probably. That's just what I think will happen, so don't panic.
Senior Member
Posts: 299
Joined: 2013-03-06
But there wasn't a quantum barrier somewhere in this scales (less than 10nm) because there was too few atoms to dope the semiconductor material as type N or P?
Will this be the new TSMC 20nm node?
http://www.kitguru.net/components/anton-shilov/samsung-vows-to-start-10nm-chip-production-in-2016-shows-first-wafers/
Guess it's been solved for 10nm. Bet afterwards they'll transition from SiO2 to SiGe. 7nm should give 50% perf over 10nm.
Who knows... there are even working 1.8nm carbon transistors. And beyond...
http://www.wired.co.uk/news/archive/2015-07/22/tiniest-processor-moores-law
Senior Member
Posts: 299
Joined: 2013-03-06
Damn, this gets exciting.
https://en.wikipedia.org/wiki/5_nanometer
Will this mark the end of silicon chips? Or a whole new approach to making transistors?