Rumored NVIDIA Next Gen-GPU codenamed Hopper gets a registered trademark
Remember a week or three ago when a rumor surfaced about a possible MCM prototype from NVIDIA called hopper? Well, that name is now a registered trademark, and guess who registered it? Yep, NVIDIA.
Next years Nvidia Ampere GPUs have not yet even been announced and now the supposedly next-generation chip generation Hopper info already spreads on the web, Hopper could be based on a multi-die design, you know chiplets.
Hopper (Grace Hopper) is the name of yet another mathematician being applied to architecture. She has been involved in groundbreaking projects, such as the Mark I super-computer (at the time) at Harvard University, and revolutionized computer science with the first high-level programming language COBOL. Now her name is supposed to adorn Nvidia's next-generation GPU: The Hopper architecture is to follow Ampere (presumably RTX 3000) and be manufactured in chiplet (MCM) design.
MCM design scale less for GPUs, think a little about SLI for example and the problems that come with it. However, it also offers significant advantages in production. The larger a chip is, the higher the risk of production error that can render the chip completely unusable (yields). MCM can create far larger packages than the limitations of one chip alone, so they are very scalable. It might be a trend for graphics chips. However, these are for the time being unconfirmed rumors, all of them.
Trademarks
So with that explained once more, this all was based on a rumor, however, NVIDIA registered 'NVIDIA Hopper' as a trademark, and also 'NVIDIA Aerial' which is related to 5G developments. On December 4th the trademarks got registered, and yeah that indicates the rumors to be valid. Hopper will follow next year's Ampere, which indeed could be MCM design but that last part remains speculation.
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Trademarking these days doesn't last unless you can prove you have commercial interest in using it within a certain time. Just recently (November iirc) a company lost it's trademark conflict in court because it could not prove (and until then never did) that they wanted to use it soon. Can't finde the link or news though, sry.
Maybe Hopper's what's coming after Ampere? Ampere in 2020 and Hopper in 2021 or so... or server grade hardware like Volta (which we never saw for gamers).
In Ireland, the global fast-food giant (and very litigious about their copyrights and names) McDonalds, lost a trademark case against an Irish fast-food place called "SuperMacs" which has been running for years here - the owner's name is MacDonagh, so obviously he had some right to use his own name in his fast-food restaurant - and the European court agreed with him! So the giant McDonalds lost the case. SuperMacs is even still able to sell burgers called "Mighty Macs" and stuff like that.
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Going to Ireland, McDonald's really should have expected to encounter something like that.
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Yep, but typical - they still tried to sue him and get him to change name of his entire chain of fast-food restaurants, and not be allowed to use his own name on them

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Not quite the same...
When a CPU core is processing some data, it generally only deals with its own L1, L2, L3 cache data, and doesn't need to access other cores L1, L2 etc data.
Whereas many GPU algorithms might need access to data which is not on the local GPU cache, so they must continually retrieve the data from other GPU caches, and this is where the difficulty, and the inefficiency lies. The cross cache communication times, and the efficiency of various GPU algorithms to minimize the amount of this data shuffling between caches is what the issue will be. Being transparent to the driver does not speed up this low level shuffling.
This is not true. Cache snooping is a key aspect of multi-core designs. A given core is not exactly accessing the other cores' caches but it has to be notified when a piece of data that both share is changed. Multiple GPUs in an SLI configuration do not. They work as independent islands. Cores in the same GPU share their caches at a block level where a block is a group of threads.
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'MCM design scale less for GPUs, think a little about SLI for example and the problems that come with it.'
I doubt this will an issue at all as the modules themselves would be transparent to the driver and appear as a single GPU as they are connected. Much like AMD's MCM CPU's appear as a single CPU.
Not quite the same...
When a CPU core is processing some data, it generally only deals with its own L1, L2, L3 cache data, and doesn't need to access other cores L1, L2 etc data.
Whereas many GPU algorithms might need access to data which is not on the local GPU cache, so they must continually retrieve the data from other GPU caches, and this is where the difficulty, and the inefficiency lies. The cross cache communication times, and the efficiency of various GPU algorithms to minimize the amount of this data shuffling between caches is what the issue will be. Being transparent to the driver does not speed up this low level shuffling.