ASUS GeForce RTX 3080 Noctua OC review
AMD Ryzen 5 5600 review
PowerColor RX 6650 XT Hellhound White review
FSP Hydro PTM Pro (1200W PSU) review
ASUS ROG Radeon RX 6750 XT STRIX review
AMD FidelityFX Super Resolution 2.0 - preview
Sapphire Radeon RX 6650 XT Nitro+ review
Sapphire Radeon RX 6950 XT Sapphire Nitro+ Pure review
Sapphire Radeon RX 6750 XT Nitro+ review
MSI Radeon RX 6950 XT Gaming X TRIO review
Next-gen AMD EPYC (Genoa) Would get 50% larger socket SP5, 96 cores and 400W TDP
AMD is seriously pounding its way into the data-center. If anything, EPYC has proven to be a very cost-effective and high-performance solution in the data-center. But what's next? Well, that would be products tagged under the development codename genoa.
Well-known twitterer ExecutableFix noticed that AMD Genoa with Zen4 core architecture would feature up to 96 cores, that's processor cores, which means 192 threads paired to 12-channel DDR5 memory. Personally, we're not too sure about the processor core count but speculated is the usage of 12 chiplets dies, each holding 8-cores and add to that the IO chip. Epyc can manage max eight channels; however, it would entail DDR5 at DDR5-4800 MHz for genoa. If you do the math scaled upwards, then this proc would also offer 160 PCIe lanes.
The new socket would be called socket SP5 and would get a tremendous amount of wires and pins with 6096 contact points. To feed all that core galore, the thermal design would change from 280 watts to 320~ 400 watts. AMD's Genoa server CPU will probably be unveiled at the end of 2022.
Teamgroup takes its memory to the next level: develops next-gen ddr5 so-dimm - 01/26/2021 10:03 AM
Teamgroup entered the validation phase with the collaboration of major motherboard manufacturers. In early 2021, it has made another breakthrough....
ThermalTake Next-Gen Toughliquid Ultra and aRGB Sync AIO CPU Liquid Coolers - 01/08/2021 10:00 AM
TOUGHLIQUID ULTRA and TOUGHLIQUID ARGB Sync are built using the TOUGHFAN 12 high-performance fans to deliver superior cooling performance and stability for system builders. Offering a variety of model...
Rumor: Next-Gen 11 Generation Intel Rocket Lake processors Gets Comet Lake mixed in - 12/20/2020 11:20 AM
Newly leaked SKU lists indicate that the Upcoming 11th Gen Intel processors will not just be based on the new Rocket Lake architecture design. Current Comet Lake generation processors would be inserte...
ASUS Launches Next-Generation ExpertBook B9 - 12/11/2020 08:42 AM
This latest ExpertBook B9 models inherit all the strong features of the previous generation. It's engineered with the latest cutting-edge up to 11th Gen Intel Core processors with built-in Intel Iris...
Qualcomm Announces Next-Generation 5G Chipset - Snapdragon 888 - 12/02/2020 09:51 AM
Qualcomm just announced its new high-end chip for Android phones, the Snapdragon 888 with an integrated 5G modem. Snapdragon 888 has 3rd gen X60 5G modem, 6th gen AI Engine and more....
Evildead666
Senior Member
Posts: 1309
Joined: 2003-09-14
Senior Member
Posts: 1309
Joined: 2003-09-14
#5891594 Posted on: 03/01/2021 11:06 AM
I get that when server has 50% more cores, it can benefit from 50% higher memory bandwidth.
But was not DDR5 supposed to deliver higher bandwidth by itself?
What would be speculated use of 12 memory channels + extra bandwidth per channel? (Conspiracy theory about drastic increase in Zen4 IPC or EPYC all core boost clock.)
Extra bandwidth available from PCIE5 devices would be my idea.
PCIE4 was pretty power hungry compared to PCIE3, and PCIE5 will be no different.
High frequencies will require more power for the moment, until it gets optimized, and maybe a lithography shrink (if that helps).
I was more expecting the CCX's to go to 12 cores rather than the extra chiplets.
Then again, with the increase in pin count, and overall 'chip' size, they would have the room.
12 memory channels/PCIE5 would mean a new IO die as well.
I get that when server has 50% more cores, it can benefit from 50% higher memory bandwidth.
But was not DDR5 supposed to deliver higher bandwidth by itself?
What would be speculated use of 12 memory channels + extra bandwidth per channel? (Conspiracy theory about drastic increase in Zen4 IPC or EPYC all core boost clock.)
Extra bandwidth available from PCIE5 devices would be my idea.
PCIE4 was pretty power hungry compared to PCIE3, and PCIE5 will be no different.
High frequencies will require more power for the moment, until it gets optimized, and maybe a lithography shrink (if that helps).
I was more expecting the CCX's to go to 12 cores rather than the extra chiplets.
Then again, with the increase in pin count, and overall 'chip' size, they would have the room.
12 memory channels/PCIE5 would mean a new IO die as well.
Bitey
Member
Posts: 33
Joined: 2018-07-15
Member
Posts: 33
Joined: 2018-07-15
#5891610 Posted on: 03/01/2021 12:45 PM
I get that when server has 50% more cores, it can benefit from 50% higher memory bandwidth.
But was not DDR5 supposed to deliver higher bandwidth by itself?
What would be speculated use of 12 memory channels + extra bandwidth per channel? (Conspiracy theory about drastic increase in Zen4 IPC or EPYC all core boost clock.)
more cores means the requirement for more independent mermory channels goes up for latency reasons and a new socket has to have the legs for quite a few years so a bit overkill now is barely adequate when the socket dies
I get that when server has 50% more cores, it can benefit from 50% higher memory bandwidth.
But was not DDR5 supposed to deliver higher bandwidth by itself?
What would be speculated use of 12 memory channels + extra bandwidth per channel? (Conspiracy theory about drastic increase in Zen4 IPC or EPYC all core boost clock.)
more cores means the requirement for more independent mermory channels goes up for latency reasons and a new socket has to have the legs for quite a few years so a bit overkill now is barely adequate when the socket dies
bnauk
Junior Member
Posts: 10
Joined: 2021-03-01
Junior Member
Posts: 10
Joined: 2021-03-01
#5891647 Posted on: 03/01/2021 03:11 PM
400W? So, matching the next gen 8 core Intel desktop CPU then. This is fine
400W? So, matching the next gen 8 core Intel desktop CPU then. This is fine
Undying
Senior Member
Posts: 18483
Joined: 2008-08-28
Senior Member
Posts: 18483
Joined: 2008-08-28
#5891649 Posted on: 03/01/2021 03:16 PM
It will support AVX3-512 instructions.
It will support AVX3-512 instructions.
Click here to post a comment for this news story on the message forum.
Senior Member
Posts: 11809
Joined: 2012-07-20
I get that when server has 50% more cores, it can benefit from 50% higher memory bandwidth.
But was not DDR5 supposed to deliver higher bandwidth by itself?
What would be speculated use of 12 memory channels + extra bandwidth per channel? (Conspiracy theory about drastic increase in Zen4 IPC or EPYC all core boost clock.)