Micron Starts Sampling GDDR5X Memory to Customers

#5249502 Posted on: 03/24/2016 10:57 AM

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Can't the manufacturers just use it for their profit by further cutting the memory bus width since less can give the same result if its faster? They seem to like doing that of late.

#5249505 Posted on: 03/24/2016 11:02 AM

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It doesn't matter though does it? Just need to make sure there's enough bandwidth available for the core - does it really matter if they do that through better VRAM or through memory bus widening?

#5249511 Posted on: 03/24/2016 11:35 AM

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GDDR5 has 170 pins per package, GDDR5X has 190 pins per package. Their prognosis for early chips is 25% higher throughput per pin.
Signaling pin count went up from 67 to 68 which does not increase complexity of PCB.

Means one chip should deliver 1.25 * 190/170 = 1.397 ~ 40% higher transfer rate than GDDR5 standard package.
Or does that mean 1.25 * 68/67 = 1.269 ~ 27% higher transfer rate than GDDR5 standard package?

Number of pins goes apparently up by ~12%. Chip is accessible in x32 and x16 mode (faster and slower). But signaling pin count stays practically same, so PCB complexity stays same per memory chip.

x16 mode is to allow communication through lower amount of traces (lower speed), but to allow another set of traces to connect another chip ("doubling" capacity per traces used).
- In reality one GDDR5X is connected in standard way and another is connected behind it (easily on other side of PCB).

I can see potential for next GTX970. While memory controller may be 384bit, 2 chips will share traces for higher capacity. I'll keep an eye on memory layout from now on when I check GDDR5X graphics cards.
- this sharing is done in following way:
- > GDDR5X uses 4 data and 4 error correction channels, has command and address bus
- > in x16 mode 1st memory chip gets 2 out of 4 data and 2 out of 4 error correction channels. 2nd chip gets another 2 of each. 1st chip gets command and address bus and relays required information to 2nd chip if appropriate (extra latency?).

Edit: Actually little correction for underlined text:
It seems that command and address bus is directly shared, so there is another logic behind which tells chips if command is for them (maybe both read required address and check if it is in their scope). (still extra latency)

#5249535 Posted on: 03/24/2016 12:57 PM

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Well this suddenly makes the recent Geforce X80 leaks very plausible.

(Lurker for many years, first post ever.)

#5249852 Posted on: 03/25/2016 07:52 AM

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GDDR5 has 170 pins per package, GDDR5X has 190 pins per package. Their prognosis for early chips is 25% higher throughput per pin.
Signaling pin count went up from 67 to 68 which does not increase complexity of PCB.

Means one chip should deliver 1.25 * 190/170 = 1.397 ~ 40% higher transfer rate than GDDR5 standard package.
Or does that mean 1.25 * 68/67 = 1.269 ~ 27% higher transfer rate than GDDR5 standard package?

Number of pins goes apparently up by ~12%. Chip is accessible in x32 and x16 mode (faster and slower). But signaling pin count stays practically same, so PCB complexity stays same per memory chip.

x16 mode is to allow communication through lower amount of traces (lower speed), but to allow another set of traces to connect another chip ("doubling" capacity per traces used).
- In reality one GDDR5X is connected in standard way and another is connected behind it (easily on other side of PCB).

I can see potential for next GTX970. While memory controller may be 384bit, 2 chips will share traces for higher capacity. I'll keep an eye on memory layout from now on when I check GDDR5X graphics cards.
- this sharing is done in following way:
- > GDDR5X uses 4 data and 4 error correction channels, has command and address bus
- > in x16 mode 1st memory chip gets 2 out of 4 data and 2 out of 4 error correction channels. 2nd chip gets another 2 of each. 1st chip gets command and address bus and relays required information to 2nd chip if appropriate (extra latency?).

Edit: Actually little correction for underlined text:
It seems that command and address bus is directly shared, so there is another logic behind which tells chips if command is for them (maybe both read required address and check if it is in their scope). (still extra latency)

Well I don't understand all that, but I have heard that GDDR5x is supposed to be offering twice the bandwidth of current GDDR5 (in addition to that same 'fact' being mentioned in this article) - through greater efficiencies mainly, but also through higher clock speeds.