AMD Next Horizon Event - Epyc 2 64 Cores - 7nm "ZEN 2" and Radeon Instinct MI60
AMD is running its 'Next Horizon' event with announcements and more details about the company's pending 7nm products are shared. The event is intended for the server and data-center centric announcements, but anything EPYC will find it's way towards the desktop as well of course.
In this news-item an overview of what is presented. AMD will be launching Radeon Instinct MI60 based on 7nm, a Hardware Virtualized GPU (via Twitter). But obviously, today is all about data-center applications, Epyc 2 at 7nm.
AMD will be previewing ROME the next-gen 7nm DataCenter EPYC CPU. The new 7nm CPU parts will be based on what we all know as ZEN2 which will offer increased IPC. (Zen had +52% IPC improvement). It was briefly mentioned that a boost of performance by 25 percent is expected (process-based), compared to Zen+. Mark Papermaster calls it a new phase of high perf. ZEN2 is now sampling and ZEN3 is on track as Papermaster mentions. ZEN3 is very likely the ZEN2 architecture, yet based on an improved fabrication process, 7nm+ (much like we all have seen with the tick/tock strategy from Intel).
ZEN2 will find its way into the market in 2019. Papermaster called it a gamechanger as well as mentioning that AMD is betting big on 7nm, as AMD felt 10nm was not the right call to make. He reconfirms the partnership with TSMC for 7nm production. (MI60)
Chiplets
The fabrication processes bring twice the density, half the power (at same perf) and 1.25x perf (at same power). It has architecture changes, like CPU Core Execution enhancements, improved branch prediction, better pre-fetching and larger op-caches. Chiplets, Zen 2 seems to feature a 14nm I/O die along with 7nm CPU chiplets (for EPYC). AMD also mentions that the process will bring great value.
AMD is updating its Infinity Fabric that connects the different dies that hold the cores. Current Epyc, Ryzen and Threadripper CPUs all are connected via the Infinity Fabric. With the Zen 2 architecture, AMD places one I/O die chip that sits in the middle, which is connected to two core dies. These are called AMD CPU chiplets, connected with the 2nd gen generation Infinity Fabric. The i/o is fabbed at 14nm process, the CPU cores (two) on 7nm, upcoming EPYC chips will include multiple Zen 2 CPU modules. Interesting addition, it supports eight DDR DRAM interfaces.
David Wang takes the stage, he is the new SVP, Engineering for the Radeon technologies group. He's talking about AMD Radeon graphics moving to the Datacenter.
Hey now, PCIe 4.0! 1TB/s bandwidth / end-to-end ECC. The MI60 based on 7nm is fitted with 32GB of HBM2 and offers Infinity Fabric GPU to GPU at 100 GB/s per link. Lots of talk about machine learning etc. It available in Q4.
AMD Rome photos courtesy of Anandtech / Toms hardware
Lisa Su has taken back the stage and is announcing up-to 64 Zen2 cores (128 threads) per socket (Rome). It has an 8-core die within the middle the 14nm IO die. It is a PCIe 4.0 capable x86 Server CPU with increased IPC. The road to Rome is through Naples (socket compatible). Lisa mentions 2x performance per socket. It can be paired with up to 4TB of DRAM. AMD was showing a demo on Rome, clearly outclassing a dual-socket Intel server system. The 64-core AMD setup was air-cooled.
A very impressive presentation on Rome alright, and again .. what goes into the data-center end up in the Desktop. 2019 is going to be a very exciting year.
That's it for this new update, we'll follow up with press releases and such in the morning.
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https://i.imgur.com/nDLZLrN.jpg
It's a workstation GPU. GV100 has 14.8 FP32 TFLOPS by comparison but it's also twice the size.
Did they mention the mm2? I cant see the presentation at work
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"It was briefly mentioned that a boost of performance by 25 percent IPC is expected, compared to Zen+."
That's way more than i expected
They said 25% from the process, I don't think they mentioned IPC? That being said they also said they had support for double load/store & FP which indicates that they now have 256 AVX2 support. I'm wondering if their target IPC increase is just going to factor that into the average.
Did they mention the mm2? I cant see the presentation at work
331mm2 - The fact that it's 300w @ 331mm2 is pretty interesting.
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And connectivity on site is lost. I had backup
Not IPC. Performance. So it is at best per core improvement (partly IPC, partly clock). And it is for EPYC. So take lowest clock of EPYC when it is under full load (all cores).
= = = =
How many people can fit into intel's safety net before it breaks and everyone falls down 22 floors? (2X cores / 4X FP performance per socket, PCIe 4.0)
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And that's what intel gets for daring to put AMD into comparison in official marketing materials and disable SMT

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"It was briefly mentioned that a boost of performance by 25 percent IPC is expected, compared to Zen+."
That's way more than i expected