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Guru3D.com » News » Leak: AMD EPYC Processors Genoa-X, New SP6 Socket, and 160 PCIe Lanes

Leak: AMD EPYC Processors Genoa-X, New SP6 Socket, and 160 PCIe Lanes

by Hilbert Hagedoorn on: 05/16/2022 08:16 AM | source: adored tv | 14 comment(s)
Leak: AMD EPYC Processors Genoa-X, New SP6 Socket, and 160 PCIe Lanes

It has been known for some time that Genoa and Bergamo CPUs will utilize Zen 4 cores manufactured using a 5nm technique. Genoa will handle up to 96 cores in addition to DDR5, PCI Express 5.0, and CXL. 

AdoredTV disclosed AMD's internal intentions, which align with the event's public details. Bergamo processors will include up to 128 customizable Zen 4c cores. Previously, AMD did not publicly disclose the number of memory channels and PCI Express lanes; however, 12 DDR5 channels have now been confirmed.

Both the SP5 and SP6 sockets are described in full by new leaks. The latter is designed for EPYC CPUs with fewer cores, less memory channels, and fewer PCI Express lanes. Torino, the generation following Genoa and Bergamo, will similarly operate on SP5 and SP6 connections. This is not surprising, considering AMD is attempting to maintain a single platform for as long as feasible. For SP5 and SP6 sockets, EPYC processors based on the Genoa and Bergamo designs will be introduced. But sockets will support CPUs differently. Socket SP5 is intended for processors with 96 or 128 cores, while socket SP6 is limited to 32 or 64 cores. It appears SP6 will be smaller, as it is designed for processors with TDPs up to 225W.

In addition to possessing fewer cores, SP6 has diminished I/O capabilities. The quantity of DDR5 memory channels has been reduced by half. The number of PCI Express 5.0 and CXL lanes has been lowered to two-thirds of the "earlier" socket.

In addition to the technical facts, AMD's plans demonstrate that the company will continue to implement its 3D cache approach with the Genoa processor. In particular, L3 cache will be increased on Genoa-X CPUs. It will be intriguing to observe the number of layers that AMD adds. In October, Genoa EPYC 7004 CPUs will enter mass manufacturing. Following Bergamo and Genoa-X in February 2023 will be Bergamo and Genoa-X. In April 2023, Zen 4 CPUs for Socket SP6 are anticipated.



Leak: AMD EPYC Processors Genoa-X, New SP6 Socket, and 160 PCIe Lanes Leak: AMD EPYC Processors Genoa-X, New SP6 Socket, and 160 PCIe Lanes Leak: AMD EPYC Processors Genoa-X, New SP6 Socket, and 160 PCIe Lanes




« Review: ASUS ROG Radeon RX 6750 XT STRIX Gaming OC · Leak: AMD EPYC Processors Genoa-X, New SP6 Socket, and 160 PCIe Lanes · EK Announces Quantum CPU Water Blocks with Walnut Wood Tops »

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reix2x
Senior Member



Posts: 563
Joined: 2010-01-20

#6017666 Posted on: 05/16/2022 03:33 PM
Thanks.
To inquire yet further, those cores, their functionality can be programmed, managed by a user?
Sorry for my ignorance, but is this similar to E (Efficiency) and P-cores (Performance) in the CPU package, buy with advanced control over them?

i think that with customizable, they meant they can customize part of the cores for certain tasks for enterprise use, lets say deep learning, financial calculations, some scientific stuff, remember these are cloud and datacenter products, so probably they will be bought by bulk

tunejunky
Senior Member



Posts: 2505
Joined: 2017-08-18

#6017672 Posted on: 05/16/2022 03:50 PM
Thanks.
To inquire yet further, those cores, their functionality can be programmed, managed by a user?
Sorry for my ignorance, but is this similar to E (Efficiency) and P-cores (Performance) in the CPU package, buy with advanced control over them?


not like Intel, these are all P cores.
the customization comes with the industry targeted. while almost all are for "the cloud", some are for hpc. and very unlike Intel all features are enabled - so "Sony", "Netflix" and "Google" can buy what they need (which is different for all three). there's also a very large market in bio-tech (CRISPR) and the energy sector.

all functions can be monitored/accessed by the end user

tunejunky
Senior Member



Posts: 2505
Joined: 2017-08-18

#6017679 Posted on: 05/16/2022 04:02 PM
I'm happy to see AMD capping at 225W for this without holding back on adding performance. I'm getting pretty annoyed with Intel and Nvidia pushing power consumption to stupid levels just so they stay on top. Granted, AMD's 6950XT was a big step in the wrong direction, so shame on them for that.



you really can't blame them (see: 3090/3080ti)
so with faster memory we get a power tweak.
with RDNA 3 we will get both (for most models except top) as the uArch improvements are on top of the node shrink
imho, i think the difference in power consumption between Lovelace and RDNA 3 will have the board tilted in AMD's favor as you'll not need those 1Kw+ PSUs, but for Nvidia you will (above 4070).
i'm looking for outstanding performance from both - but back on the industrial side this means that compliance with Paris Accords is out of the question for the Quadro line but the Instinct isn't.
this makes a difference in EU corporate sales depending on the scale of use.

Kaarme
Senior Member



Posts: 2978
Joined: 2013-03-10

#6017717 Posted on: 05/16/2022 05:40 PM
this makes a difference in EU corporate sales depending on the scale of use.


Towards the real heavyweight (data center) users, can't they actually avoid limitations if they can put the waste heat to some use? Like industrial use or district heating?

user1
Senior Member



Posts: 2057
Joined: 2016-01-29

#6017775 Posted on: 05/16/2022 09:10 PM
Thanks.
To inquire yet further, those cores, their functionality can be programmed, managed by a user?
Sorry for my ignorance, but is this similar to E (Efficiency) and P-cores (Performance) in the CPU package, but with advanced control over them?
afaik they have the same instruction set, they are both performance designs, they are just tuned for their specific niche, bergamo is basically just uses a more die space efficient version of zen4 core , which lets them pack more cores in. with maybe some tuning specific for cloud/server workloads. there won't be any chips with both core types on the same package most likely.

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