Intel to disable insecure TSX feature on older CPUs
Intel has decided to deactivate Transactional Sync Extensions in Skylake, Kaby Lake, Coffee Lake and Whiskey Lake processor chips. Intel deactivates the feature because of memory ordening errors and .. hackers can exploit it.
New kernel patches will disable TSX in a micro-update for the CPU soon. Deactivating TSX in some tasks will result in lower performance in older chips.TSX adds hardware transactional memory support to the CPUs, giving them up to 40 percent better performance in certain tasks. TSX has been in chips based on the Haswell microarchitecture since the Skylake generation in 2013.
In 2016, it was discovered that TSX could be exploited for a side-channel timing attack, where hackers could break kernal address space layout randomization, or KASLR, to gain access to a system. That's one of the reasons the feature is no longer supported.
TSX also can cause an error in the memory ordering, i.e. the sequence of accessing memory. At the beginning of this month, Intel published a white paper. This is known as a problem since 2018 and is disabled with SGX and SMM. With the micro-update, TSX can no longer be accessed and there is no workaround in the Linux kernel.
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Senior Member
Posts: 3397
Joined: 2007-05-31
nearly none (as exept bug it already bring nearly none).
Sometime something big on paper isn't so great in real condition.
Senior Member
Posts: 2468
Joined: 2016-08-01
nearly none (as exept bug it already bring nearly none).
Sometime something big on paper isn't so great in real condition.
Ok at least this is something still sucks but even if people really have to disable it they will not loose perfomance

Senior Member
Posts: 13119
Joined: 2014-07-21
So Haswell keeps it? Making it probably faster than the CPUs later on... oh Intel, you and your after sale cuts to performance because of "security" reasons.
Senior Member
Posts: 12905
Joined: 2003-05-24
yah more thing cripple my cpu?
According Hwinfo I have TXS enabled and running.
Dont see how disabling thing would make compatible but then again it security flaw? that been around since 2016? that intel is just now "disabling"
Senior Member
Posts: 207
Joined: 2005-08-31
TSX was problematic from its first iteration in Haswell. The RPCS3 emulator still supports it, but it's disabled by default and not recommended to be forced on due to possibility of fatal data corruption.
It's a nice performance feature to have, particularly with multi-thread intensive code, but implementation and validation in hardware is rather tricky and the strict memory ordering in x86 certainly makes it extra demanding.