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Intel Likely Starts 10nm Volume Production in the second half of 2018
Intel is pushing hard with the production of 10nm processors, the chip yield is currently low, Intel delivers only a few CPUs to partners. Ice Lake is expected to appear in 2019.
The 10-nm series production is scheduled to start at Intel in the second half of 2018, which has announced CEO Brian Krzanich in discussing the results of the fourth quarter of 2017 mentions Golem. According to Krzanich, in the coming months, the chip yield (yield) will be increased dramatically for proper mass production, the manufacturer so far has sent only limited samples of Cannon Lake U to close partners.
Apparently, the plan is to switch from 10 nm to 10+ nm as quickly as possible, a slightly improved version of the fabrication node. Ice Lake is to be created with this production technology. Intel intends to use these processors in all segments from the tablet to up-to supercomputer.
For Ultrabooks, Intel is planning a follow-up to Whiskey Lake for Kaby Lake Refresh , another 15-watt quad-core. In addition to a 4 + 2 design with four cores and GT2 graphics unit is also one with 4 + 3 planned, but then called Coffee Lake U. This design uses a GT3, the more shader cores and also EDRAM as a fast On -Package memory uses. Whiskey Lake U and Coffee Lake U are apparently manufactured at 14++ nm.
For a higher class of performance, the Coffee Lake H are planned, which are Hexacore chips with 45 watts of thermal loss. They follow Kaby Lake H with four cores and are said to clock very high at up to 4.8 GHz . Top model will probably be the Core i9-8950HK with open multiplier for notebook overclockers. Thus far Intel uses the Core i9 designation only for desktop chips like the Core i9-7980XE with 18 CPU cores.
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Intel is likely to
NaturalViolence
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Posts: 77
Joined: 2009-10-01
#5515132 Posted on: 01/29/2018 01:26 PM
Because transistors are not cubes. They have odd shapes and are susceptible to interference or electron tunneling if placed too close to one another. The drop is measured size vs. die area depends on which axis were shrunk and by how much. Their "size" is also measured differently by different companies. Intel's 14nm process is smaller than global foundries 14nm (which would be about 18nm if they were measured the way Intel measures). To get a better picture of the possible density we need to know the exact size along all three axis as well as the required void space between components to know how much area they use and how closely they can be packed. At the moment those details aren't available yet for the 10nm process, just the density.
That graph is strange... how does moving from 14nm to 10nn more than double the transistor density(40mio/mm² @ 14nm -> 100mio/mm² @ 10nm = -28% size, 2.5x density)? Especially if the previous larger shrinks only allowed for a smaller improvement (18mio/mm² @ 22nm -> 40mio/mm² @ 14nm = -36% size, 2.22x density)
Because transistors are not cubes. They have odd shapes and are susceptible to interference or electron tunneling if placed too close to one another. The drop is measured size vs. die area depends on which axis were shrunk and by how much. Their "size" is also measured differently by different companies. Intel's 14nm process is smaller than global foundries 14nm (which would be about 18nm if they were measured the way Intel measures). To get a better picture of the possible density we need to know the exact size along all three axis as well as the required void space between components to know how much area they use and how closely they can be packed. At the moment those details aren't available yet for the 10nm process, just the density.
JamesSneed
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Posts: 618
Joined: 2017-02-14
#5515231 Posted on: 01/29/2018 07:00 PM
Also recall when Intel moved to using FinFets back when they were at 22nm ie "transistors in the 3d dimension" they called it. People gloss over this all the time but now chips are 3d the nanometers taken from the smallest feature the lithography can make really doesn't mean much anymore. It meant a lot more back when chips were "2d" since it directly contributed to the gate length which had a fairly predictable shrink but it was mostly marketing then too. So the little fins that stick up like a microscopic sharks fin contribute a lot to density as well. Instead of just measuring width you now have to account for the length and the pitch or what angle the pieces lean over on the 3d pieces. I tried to keep this rather high level on purpose. The short of it is lithography feature size doesn't translate to densities anymore since chips are now in 3d.
Also recall when Intel moved to using FinFets back when they were at 22nm ie "transistors in the 3d dimension" they called it. People gloss over this all the time but now chips are 3d the nanometers taken from the smallest feature the lithography can make really doesn't mean much anymore. It meant a lot more back when chips were "2d" since it directly contributed to the gate length which had a fairly predictable shrink but it was mostly marketing then too. So the little fins that stick up like a microscopic sharks fin contribute a lot to density as well. Instead of just measuring width you now have to account for the length and the pitch or what angle the pieces lean over on the 3d pieces. I tried to keep this rather high level on purpose. The short of it is lithography feature size doesn't translate to densities anymore since chips are now in 3d.
Roger_D25
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Senior Member
Posts: 4384
Joined: 2004-12-13
#5516161 Posted on: 02/01/2018 06:45 PM
Great explanation guys, thanks for helping us better understand what is going on!
Great explanation guys, thanks for helping us better understand what is going on!
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That graph is strange... how does moving from 14nm to 10nn more than double the transistor density(40mio/mm² @ 14nm -> 100mio/mm² @ 10nm = -28% size, 2.5x density)? Especially if the previous larger shrinks only allowed for a smaller improvement (18mio/mm² @ 22nm -> 40mio/mm² @ 14nm = -36% size, 2.22x density)