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Infinity fabric clock uplift would make DDR4-4000 possible for Zen 3
A leaked slide shows that the upcoming Ryzen 5000 chips should be able to achieve higher infinity fabric clock speeds compared to their predecessors. Turkish website Technopat mentions this.
The slide claims that ddr4-4000 is to Ryzen 5000 what ddr4-3800 was to Ryzen 3000. That speed was relevant with the Zen 2 chips because it was generally the highest possible memory speed with the infinity fabric in 1: 1 mode. This also seems to be the case for Ryzen 5000: according to the slide, memory and fabric clock is the most cost-effective method for tinkering with the chips. Since ddr4-4000 has an actual clock speed of 2,000 MHz, that means that that speed can in all probability be (reasonably) achievable.
Memory management in AMD Ryzen processors is divided into three basic elements. The memory controller used by AMD and Infinity Fabric management, which manages the components within the CPU, is very important.
- Infinity Fabric Clock (fclk) : Manages how fast CPU cores can communicate with CPU components and SoC controllers. (Such as PCIe, SATA, USB)
- Memory Controller Clock (uclk) : Manages how fast the memory controller can receive / transfer commands from RAM.
- Memory Clock (mclk) : Frequency of main system memory.
As a result, RAMs will work more stable with new generation Ryzen processors. Thus, users will be able to reach higher frequencies and make fine adjustments.
DDR4-3600 remains the "sweet spot" and AMD's recommendation for the Zen 3-based processors, which are also specified with up to DDR4-3200. The new optimum, however, is DDR4-4000 with a synchronous IF or fabric clock (FCLK) and memory controller clock (ULCK) of 2,000 MHz.
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Uroshi
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#5843230 Posted on: 10/16/2020 08:26 AM
I thought the memory controller was exactly the same as in the 3000 series. Same IO die. Were the chiplets the ones limiting the clock rate?
I thought the memory controller was exactly the same as in the 3000 series. Same IO die. Were the chiplets the ones limiting the clock rate?
wavetrex
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Posts: 1236
Joined: 2008-07-16
#5843233 Posted on: 10/16/2020 08:41 AM
IF sits between the IO die and CCDs.
I/O die was already capable of much faster memory speeds, plenty of overclockers went beyond DDR4-5000 (2500Mhz) ... however, that was done with 2:1 ratio (memory:IF), because IF on Zen2 doesn't scale beyond 1900 Mhz, that's about the max.
If the new CCDs have a better structure (for example, with the IF portion on the side instead of in the center, the IF links themselves may be a few millimetres shorter), allowing for that little bit of extra speed.
Zen 2 ( all the I/O is smack in the middle, with cores on the sides)
The IF had to travel from the middle UNDER half of the cache, and then converge on the I/O die:
Zen 3 ( I/O is on one of the sides, most likely towards the I/O die )
The length of the links themselves is most likely reduced by 30-40% !!
And by the way his picture looks, there's a big-ass wide crossbar right in the middle of the die, that seems a very VERY wide bus !
(Probably also how they managed to improve power efficiency, the X-bar is (much) wider and lower clocked, so consumes less power)
Final edit:
It will be interesting to see how this is arranged on the EPYC / Threadripper, with the asymmetrical CCD ...
With Zen 2 EPYC, the CCDs could sit right near each other, as the IF were coming down from the middle:
1, 2 __ 5, 6
==><==
3, 4 __ 7, 8
But with the new layout, that will not be possible anymore... so new EPYC will clearly look a bit different than current one !
IF sits between the IO die and CCDs.
I/O die was already capable of much faster memory speeds, plenty of overclockers went beyond DDR4-5000 (2500Mhz) ... however, that was done with 2:1 ratio (memory:IF), because IF on Zen2 doesn't scale beyond 1900 Mhz, that's about the max.
If the new CCDs have a better structure (for example, with the IF portion on the side instead of in the center, the IF links themselves may be a few millimetres shorter), allowing for that little bit of extra speed.
Zen 2 ( all the I/O is smack in the middle, with cores on the sides)
The IF had to travel from the middle UNDER half of the cache, and then converge on the I/O die:
Zen 3 ( I/O is on one of the sides, most likely towards the I/O die )
The length of the links themselves is most likely reduced by 30-40% !!
And by the way his picture looks, there's a big-ass wide crossbar right in the middle of the die, that seems a very VERY wide bus !
(Probably also how they managed to improve power efficiency, the X-bar is (much) wider and lower clocked, so consumes less power)
Final edit:
It will be interesting to see how this is arranged on the EPYC / Threadripper, with the asymmetrical CCD ...
With Zen 2 EPYC, the CCDs could sit right near each other, as the IF were coming down from the middle:
1, 2 __ 5, 6
==><==
3, 4 __ 7, 8
But with the new layout, that will not be possible anymore... so new EPYC will clearly look a bit different than current one !
nizzen
Senior Member
Posts: 1191
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Senior Member
Posts: 1191
Joined: 2005-08-05
#5843247 Posted on: 10/16/2020 09:28 AM
If you have 3200c14 b-die, they will pretty much overclock to whatever zen 3 can do with 1:1 infinity fabric
I knew we gonna need a new ram kit with zen3, 3200 is not gonna cut it. 4000mhz cl19 costs 290Eur here atm which isnt that bad.
If you have 3200c14 b-die, they will pretty much overclock to whatever zen 3 can do with 1:1 infinity fabric
Undying
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Posts: 13903
Joined: 2008-08-28
#5843249 Posted on: 10/16/2020 09:32 AM
Nah its a cl16 c die i think, gskill aegis is crap. I'll need a new kit. There is plenty of b die 3600 for cheaper so maybe get that one and overclock it.
If you have 3200c14 b-die, they will pretty much overclock to whatever zen 3 can do with 1:1 infinity fabric
Nah its a cl16 c die i think, gskill aegis is crap. I'll need a new kit. There is plenty of b die 3600 for cheaper so maybe get that one and overclock it.
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I knew we gonna need a new ram kit with zen3, 3200 is not gonna cut it. 4000mhz cl19 costs 290Eur here atm which isnt that bad.