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GobalFoundries 12LP+ FinFET solution ready for production
There's yet another optimization enhancement at 12nm, GobalFoundries has announced that its most advanced FinFET solution, the 12LP+, has completed technology qualification and is ready for production.
The foundry's 12LP+ solution is optimised for artificial intelligence (AI) training and inference applications.
Built on a proven platform with a robust production ecosystem, the 12LP+ introduces new features including an updated standard cell library, an interposer for 2.5D packaging, and a low-power 0.5V Vmin SRAM bitcell that supports the low latency and power-efficient shuttling of data between the AI processors and memory. The result is a semiconductor solution that has been specifically engineered to meet the needs of the fast-growing AI market.
“Artificial intelligence is on a trajectory to become the most disruptive technology of our lifetime,” said Amir Faintuch, senior vice president and general manager of Computing and Wired Infrastructure at GF. “It is increasingly clear that the power efficiency of AI systems – in particular how many operations you can wrest from a watt of power – will be among the most critical factors a company considers when deciding to invest in data centres or edge AI applications. Our new 12LP+ solution tackles this challenge head-on. It has been engineered and optimised, obsessively so, with AI in mind.”
By partnering closely and learning from existing AI clients, GF has developed the 12LP+ to provide greater differentiation and increased value for designers in the AI space while minimising their development and production costs.
Driving the enhanced performance of 12LP+ are features including a 20-percent SoC-level logic performance boost over 12LP, and a 10-percent improvement in logic area scaling. These advancements are achieved in 12LP+ through its next-generation standard cell library with performance-driven area optimized components, single Fin cells, a new low-voltage SRAM bitcell, and improved analogue layout design rules.
12LP+ is also augmented by GF’s AI design reference package, as well as GF’s co-development, packaging, and post-fab turnkey services. Close collaboration between GF and its ecosystem partners has resulted in cost-effective development costs and a quicker time to market.
GF said that it will expand the IP validations for 12LP+ to include PCIe 3/4/5 and USB 2/3 to host processors, HBM2/2e, DDR/LPDDR4/4x and GDDR6 to external memory, and chip-to-chip interconnect for designers and clients pursuing chiplet architectures.
GFs’ 12LP+ solution has been qualified and is now ready for production at GF’s Fab 8 in Malta, New York. Several 12LP+ tape-outs are scheduled for the second half of 2020.
SplashDown
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#5805284 Posted on: 07/02/2020 05:38 PM
1. A bigger die means fewer usable chips can be made per-wafer. Remember, the wafers are circular, so anything that gets cropped by the circle is basically rendered useless. I can't imagine these wafers are cheap.
. Why can't they make them square? I know nothing about this process but i understand what your saying about the circle.
1. A bigger die means fewer usable chips can be made per-wafer. Remember, the wafers are circular, so anything that gets cropped by the circle is basically rendered useless. I can't imagine these wafers are cheap.
. Why can't they make them square? I know nothing about this process but i understand what your saying about the circle.
schmidtbag
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#5805300 Posted on: 07/02/2020 06:27 PM
Good question - I've wondered the same.
Why can't they make them square? I know nothing about this process but i understand what your saying about the circle.
Good question - I've wondered the same.
GlennB
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#5805364 Posted on: 07/02/2020 09:50 PM
One of the biggest reasons that wafers are round is because they are in that shape from the beginning. The silicon ingots that are used to grow the wafer are circular in shape. This is due to the process of dipping a seed crystal into molten silicon and rotating and slowly extracting as the crystal grows. This is also known as the popular
Why can't they make them square? I know nothing about this process but i understand what your saying about the circle.
Good question - I've wondered the same.
One of the biggest reasons that wafers are round is because they are in that shape from the beginning. The silicon ingots that are used to grow the wafer are circular in shape. This is due to the process of dipping a seed crystal into molten silicon and rotating and slowly extracting as the crystal grows. This is also known as the popular
Czochralski method.
Since the product is already circular in shape, the wafers are cut into that same shape. While they could be cut into a different shape, it would waste silicon.
RED.Misfit
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#5805369 Posted on: 07/02/2020 10:02 PM
There are still a lot of products being tapped on 12nm, 22nm & even 28nm (and probably bigger node, way bigger). Not every product needs the last cutting edge node.
Both Intel & TSMC kept old node to tape out specific products for specific clients (okay Intel is probably still its own client even on older node)
There are still a lot of products being tapped on 12nm, 22nm & even 28nm (and probably bigger node, way bigger). Not every product needs the last cutting edge node.
Both Intel & TSMC kept old node to tape out specific products for specific clients (okay Intel is probably still its own client even on older node)
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AMD said IO doesn't scale well with node so making it cheaper would benefit both them and the consumer. They didn't need the extra space anyway for Zen 2, so going that route was the best of both engineering and economics.
That said, they had a big contract with GF for their production and could not afford cancel. As Ryzen needed to move forward in node (for competition sake) and GF wouldn't have a 7nm one, TSMC 7nm was chosen.
It's true that IO die is taking up enormous space (not relevant on sTRX4 but very much so on AM4), I predict that as soon as possible it will transit to 7nm: probably with Zen 4 on 5nm.
Yeah, the IO die doesn't really do anything computationally expensive relative to the cores, so I can see how it was more economical to just stick with 12nm. I don't necessarily think there was a problem with them using 12nm for that, but rather, they're going to need to shrink that die if they intend to do more. That being said, for now they don't need the extra space on TR or Epyc, but if they intend to add more than 64 cores, they're going to need more space. The IO die for those are so big that they might actually be a bit cost ineffective. Seems to me the price of each die is correlated with the total area of the die. I can think of 2 reasons for this:
1. A bigger die means fewer usable chips can be made per-wafer. Remember, the wafers are circular, so anything that gets cropped by the circle is basically rendered useless. I can't imagine these wafers are cheap.
2. The bigger the die, the more likely there will be an imperfection. I'm not sure you can bin these IO dies since AMD seems to only have 2 variants of them. That means a faulty die isn't an option, making faults more costly.
So, although the IO die might not really gain much of a functional benefit from a smaller node, it will allow for other improvements.
If the thing about the contract is true, I wonder what kind of rank amateur was the one negotiating the contract. You'd think there would have been a clause in the contract stipulating GF must remain competitive in the market for the contract to apply. So, when GF abandoned the 7nm race, a sensible contract would have been void. That being said, perhaps there is such a clause, but it had a very lax time limit.
Well, that kinda did happen. AMD wanted 7nm, GF was like "nah", and so AMD moved their CPU core production to TSMC. To my recollection, they went to GF entirely for Zen and Zen+.