DeepCool LS720 (LCS) review
Fractal Design Pop Air RGB Black TG review
Palit GeForce GTX 1630 4GB Dual review
FSP Dagger Pro (850W PSU) review
Razer Leviathan V2 gaming soundbar review
Guru3D NVMe Thermal Test - the heatsink vs. performance
EnGenius ECW220S 2x2 Cloud Access Point review
Alphacool Eisbaer Aurora HPE 360 LCS cooler review
Noctua NH-D12L CPU Cooler Review
Silicon Power XPOWER XS70 1TB NVMe SSD Review
Documents show AMD AM5 will use DDR5 and PCI-E 4.0, not 5.0
According to new documents stolen during the attack on Gigabyte, the AM5 platform's I/O scheme has been published, revealing that 600 Series motherboards would use DDR5 memory and that PCI-E 4.0 will continue to be used, at least in Ryzen 7000s.
Specifically, it verifies that DDR5 memories will be supported in Dual Channel configuration, allowing a maximum of four RAM modules to be installed, as has been typical in “Mainstream” platforms for many years. There will be 16 lines dedicated to GPUs on the other side of the PCI-Express 4.0 lines coming from the CPU, 4 lines for an M.2 NVME SSD, and another 4 lines for a USB 4.0 controller that will also have a Displayport connection to allow it to work in alt-mode. There will also be a Displayport connection to allow it to work in alt-mode. Two video outputs, two USB 2.0 ports, one USB 3.2 Gen2 port, sound connections, and the connections for the BIOS are among the other connections that come out of the processor.
A number of PCI-E 4.0 lanes will be available on the chipset's side, which will be connected to the CPU by four PCI-E 4.0 lanes. These will be used for NVME ports, LAN, Wi-Fi modules, and other peripherals, as well as support for 10Gbps and 20Gbps USB 3.2, USB2 compatibility, and numerous SATA ports.
As a result, aside from support for DDR5 and USB4, there will be no significant changes in the I / O when compared to AM5. It will be interesting to observe when it transitions to PCI-E 5.0, which may not occur until the Ryzen 8000 or 9000 series processors are used in conjunction with the 700 or 800 Series motherboards.
Massive Databreach hits Intel, confidential documentation about processors leaks away - 08/07/2020 09:09 AM
Yet another setback for Intel, it is confirmed that Intel was hit by a data breach, an extensive one where 20 GB of documentation including chip designs and code has leaked away....
Intel confirms large LGA1700 socket for Alder Lake In Developer Document - 06/29/2020 08:19 AM
Although not announced or done deliberately, some technical documentation popped up showing that Alder Lake, the processors following Rocket Lake, is indeed based on a Socket LGA 1700 de`sign, which m...
GeForce RTX Mobile Shows up in Chinese OEM documentation - 12/27/2018 10:55 AM
I think it is safe to say that there will be a number of announcements at CES from NVIDIA, including mobile RTX 2060, 2070 and 2080 parts. A Chinese OEM party with the name of CJSCOPE is actively list...
Intel Documents shows two eight-core Coffee Lake based processors - 05/25/2018 01:21 PM
Intel has a downloadable technical database, shows and for sure reaffirms at least two eight-core Coffee Lake processor, it also shows TDP at 95 and 80 watts. The desktop part will be a 95W model, th...
AMD Document Is Listing More Ryzen, but also Threadripper 29x0 Zen+ Processors - 04/28/2018 08:00 PM
It's quite difficult to spot and decipher, but it seems valid. More 12nm Zen+ Ryzen processors are planned by AMD, but also Threadripper will see new proc launches based on the refresh as well as mob...
Kaarme
Senior Member
Posts: 2955
Joined: 2013-03-10
Senior Member
Posts: 2955
Joined: 2013-03-10
#5940205 Posted on: 08/22/2021 11:17 PM
I wonder if something like 1GB of HBM within the CPU, among the chiplets, as a sort of L4 cache, could replace increased memory channels?
Edit: I forgot AMD was already experimenting with the 3D packing to add a massive (?) cache.
What I think is more of a problem is that they're sticking with dual channel memory. For desktop CPUs, that doesn't really matter, but this will matter when it comes to APUs. DDR5 is a step in the right direction but I don't think it'll be enough.
I wonder if something like 1GB of HBM within the CPU, among the chiplets, as a sort of L4 cache, could replace increased memory channels?
Edit: I forgot AMD was already experimenting with the 3D packing to add a massive (?) cache.
schmidtbag
Senior Member
Posts: 6575
Joined: 2012-11-10
Senior Member
Posts: 6575
Joined: 2012-11-10
#5940214 Posted on: 08/23/2021 12:06 AM
I wonder if something like 1GB of HBM within the CPU, among the chiplets, as a sort of L4 cache, could replace increased memory channels?
Edit: I forgot AMD was already experimenting with the 3D packing to add a massive (?) cache.
The problem with that is the chips could become really expensive.
Valve managed to get quad-channel for the Deck on an APU, so, it's not like AMD can't achieve this for a reasonable price.
I didn't hear whether AMD was doing 3D stacking, but I know Intel is, and AMD knows that if they want to stay competitive, they'll have to do the same. I'm still curious how that stacking will work in terms of cooling. Intel lapping their dies was enough to keep clock speeds higher on their 10th gen CPUs. You can't lap the transistors though, and unlike that top layer being shaved off, the additional transistor layers will produce heat. Sure will get interesting, that's for sure.
I wonder if something like 1GB of HBM within the CPU, among the chiplets, as a sort of L4 cache, could replace increased memory channels?
Edit: I forgot AMD was already experimenting with the 3D packing to add a massive (?) cache.
The problem with that is the chips could become really expensive.
Valve managed to get quad-channel for the Deck on an APU, so, it's not like AMD can't achieve this for a reasonable price.
I didn't hear whether AMD was doing 3D stacking, but I know Intel is, and AMD knows that if they want to stay competitive, they'll have to do the same. I'm still curious how that stacking will work in terms of cooling. Intel lapping their dies was enough to keep clock speeds higher on their 10th gen CPUs. You can't lap the transistors though, and unlike that top layer being shaved off, the additional transistor layers will produce heat. Sure will get interesting, that's for sure.
CPC_RedDawn
Senior Member
Posts: 9356
Joined: 2008-01-06
Senior Member
Posts: 9356
Joined: 2008-01-06
#5940216 Posted on: 08/23/2021 12:13 AM
I didn't hear whether AMD was doing 3D stacking, but I know Intel is, and AMD knows that if they want to stay competitive, they'll have to do the same.
schmidtbag
Senior Member
Posts: 6575
Joined: 2012-11-10
Senior Member
Posts: 6575
Joined: 2012-11-10
#5940222 Posted on: 08/23/2021 01:07 AM
Good to know, though, this is a bit a way away from the 1GB HBM, or what Intel is doing with Foveros. It is a great step forward though, and I imagine caches don't run as hot so stacking them shouldn't e a problem.
Good to know, though, this is a bit a way away from the 1GB HBM, or what Intel is doing with Foveros. It is a great step forward though, and I imagine caches don't run as hot so stacking them shouldn't e a problem.
Click here to post a comment for this news story on the message forum.
Senior Member
Posts: 6575
Joined: 2012-11-10
I couldn't care less that it doesn't have PCIe 5.0. 4.0 had some practical advantages over 3.0, even if the x16 slots still aren't necessary, but we're still several years away from saturating 4.0 to any degree that actually matters. SSDs are the only thing that could possibly saturate all that bandwidth, but if that's the case then just get a x8 or x16 SSD instead of a M.2.
What I think is more of a problem is that they're sticking with dual channel memory. For desktop CPUs, that doesn't really matter, but this will matter when it comes to APUs. DDR5 is a step in the right direction but I don't think it'll be enough.